From 441717c46fc71e349cf8373392a2afd61332dd4e Mon Sep 17 00:00:00 2001 From: Bartosz Dudziak Date: Thu, 16 Jul 2020 22:55:28 +0200 Subject: dt-bindings: pinctrl: qcom: Add msm8226 pinctrl bindings Add device tree binding Documentation details for Qualcomm msm8226 pinctrl driver. - Bindings documentation was based on qcom,ipq6018-pinctrl.yaml added by Sricharan R and then modified for msm8226 content Signed-off-by: Bartosz Dudziak Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20200716205530.22910-2-bartosz.dudziak@snejp.pl Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,msm8226-pinctrl.yaml | 132 +++++++++++++++++++++ 1 file changed, 132 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml new file mode 100644 index 000000000000..1f0f5757f9e1 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,msm8226-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. MSM8226 TLMM block + +maintainers: + - Bjorn Andersson + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + MSM8226 platform. + +properties: + compatible: + const: qcom,msm8226-pinctrl + + reg: + description: Specifies the base address and size of the TLMM register space + maxItems: 1 + + interrupts: + description: Specifies the TLMM summary IRQ + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + description: Specifies the PIN numbers and Flags, as defined in + include/dt-bindings/interrupt-controller/irq.h + const: 2 + + gpio-controller: true + + '#gpio-cells': + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-reserved-ranges: + maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: "/schemas/pinctrl/pincfg-node.yaml" + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-6])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. Functions are only valid for gpio pins. + enum: [ gpio, cci_i2c0, blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim5, + blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c5, blsp_spi1, + blsp_spi2, blsp_spi3, blsp_spi5, blsp_uart1, blsp_uart2, + blsp_uart3, blsp_uart5, cam_mclk0, cam_mclk1, wlan ] + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + required: + - pins + - function + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + msmgpio: pinctrl@fd510000 { + compatible = "qcom,msm8226-pinctrl"; + reg = <0xfd510000 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&msmgpio 0 0 117>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + + serial-pins { + pins = "gpio8", "gpio9"; + function = "blsp_uart3"; + drive-strength = <8>; + bias-disable; + }; + }; -- cgit v1.2.3-59-g8ed1b From aebebcf910c4d7b6b98bc7b3b573ec24543861a6 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Mon, 3 Aug 2020 17:20:54 +0300 Subject: dt-bindings: pinctrl: Add bindings for Actions S500 SoC Add pinctrl and gpio bindings for Actions Semi S500 SoC. Signed-off-by: Cristian Ciocaltea Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/7abf618c446b7b648f512afe72e46704156e9912.1596461275.git.cristian.ciocaltea@gmail.com Signed-off-by: Linus Walleij --- .../bindings/pinctrl/actions,s500-pinctrl.yaml | 240 +++++++++++++++++++++ 1 file changed, 240 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml new file mode 100644 index 000000000000..33391d30c00c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml @@ -0,0 +1,240 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/actions,s500-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Actions Semi S500 SoC pinmux & GPIO controller + +maintainers: + - Manivannan Sadhasivam + - Cristian Ciocaltea + +description: | + Pinmux & GPIO controller manages pin multiplexing & configuration including + GPIO function selection & GPIO attributes configuration. Please refer to + pinctrl-bindings.txt in this directory for common binding part and usage. + +properties: + compatible: + const: actions,s500-pinctrl + + reg: + items: + - description: GPIO Output + GPIO Input + GPIO Data + - description: Multiplexing Control + - description: PAD Pull Control + PAD Schmitt Trigger Enable + PAD Control + - description: PAD Drive Capacity Select + minItems: 1 + maxItems: 4 + + clocks: + maxItems: 1 + + gpio-controller: true + + gpio-ranges: + maxItems: 1 + + '#gpio-cells': + description: + Specifies the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + interrupt-controller: true + + '#interrupt-cells': + description: + Specifies the pin number and flags, as defined in + include/dt-bindings/interrupt-controller/irq.h + const: 2 + + interrupts: + description: + One interrupt per each of the 5 GPIO ports supported by the controller, + sorted by port number ascending order. + minItems: 5 + maxItems: 5 + +patternProperties: + '-pins$': + type: object + patternProperties: + '^(.*-)?pinmux$': + type: object + description: + Pinctrl node's client devices specify pin muxes using subnodes, + which in turn use the standard properties below. + $ref: pinmux-node.yaml# + + properties: + groups: + description: + List of gpio pin groups affected by the functions specified in + this subnode. + items: + oneOf: + - enum: [lcd0_d18_mfp, rmii_crs_dv_mfp, rmii_txd0_mfp, + rmii_txd1_mfp, rmii_txen_mfp, rmii_rxen_mfp, rmii_rxd1_mfp, + rmii_rxd0_mfp, rmii_ref_clk_mfp, i2s_d0_mfp, i2s_pcm1_mfp, + i2s0_pcm0_mfp, i2s1_pcm0_mfp, i2s_d1_mfp, ks_in2_mfp, + ks_in1_mfp, ks_in0_mfp, ks_in3_mfp, ks_out0_mfp, + ks_out1_mfp, ks_out2_mfp, lvds_o_pn_mfp, dsi_dn0_mfp, + dsi_dp2_mfp, lcd0_d17_mfp, dsi_dp3_mfp, dsi_dn3_mfp, + dsi_dp0_mfp, lvds_ee_pn_mfp, spi0_i2c_pcm_mfp, + spi0_i2s_pcm_mfp, dsi_dnp1_cp_mfp, lvds_e_pn_mfp, + dsi_dn2_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp, + uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp, + sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_mfp, + uart0_rx_mfp, clko_25m_mfp, csi_cn_cp_mfp, sens0_ckout_mfp, + uart0_tx_mfp, i2c0_mfp, csi_dn_dp_mfp, sen0_pclk_mfp, + pcm1_in_mfp, pcm1_clk_mfp, pcm1_sync_mfp, pcm1_out_mfp, + dnand_data_wr_mfp, dnand_acle_ce0_mfp, nand_ceb2_mfp, + nand_ceb3_mfp] + minItems: 1 + maxItems: 32 + + function: + description: + Specify the alternative function to be configured for the + given gpio pin groups. + enum: [nor, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0, + sens1, uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, + i2s1, pcm1, pcm0, ks, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, + p0, sd0, sd1, sd2, i2c0, i2c1, i2c3, dsi, lvds, usb30, clko_25m, + mipi_csi, nand, spdif, ts, lcd0] + + required: + - groups + - function + + additionalProperties: false + + '^(.*-)?pinconf$': + type: object + description: + Pinctrl node's client devices specify pin configurations using + subnodes, which in turn use the standard properties below. + $ref: pincfg-node.yaml# + + properties: + groups: + description: + List of gpio pin groups affected by the drive-strength property + specified in this subnode. + items: + oneOf: + - enum: [sirq_drv, rmii_txd01_txen_drv, rmii_rxer_drv, + rmii_crs_drv, rmii_rxd10_drv, rmii_ref_clk_drv, + smi_mdc_mdio_drv, i2s_d0_drv, i2s_bclk0_drv, i2s3_drv, + i2s13_drv, pcm1_drv, ks_in_drv, ks_out_drv, lvds_all_drv, + lcd_dsi_drv, dsi_drv, sd0_d0_d3_drv, sd1_d0_d3_drv, + sd0_cmd_drv, sd0_clk_drv, sd1_cmd_drv, sd1_clk_drv, + spi0_all_drv, uart0_rx_drv, uart0_tx_drv, uart2_all_drv, + i2c0_all_drv, i2c12_all_drv, sens0_pclk_drv, + sens0_ckout_drv, uart3_all_drv] + minItems: 1 + maxItems: 32 + + pins: + description: + List of gpio pins affected by the bias-pull-* and + input-schmitt-* properties specified in this subnode. + items: + oneOf: + - enum: [dnand_dqs, dnand_dqsn, eth_txd0, eth_txd1, eth_txen, + eth_rxer, eth_crs_dv, eth_rxd1, eth_rxd0, eth_ref_clk, + eth_mdc, eth_mdio, sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0, + i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, + i2s_mclk1, ks_in0, ks_in1, ks_in2, ks_in3, ks_out0, ks_out1, + ks_out2, lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp, + lvds_ocn, lvds_obp, lvds_obn, lvds_oap, lvds_oan, lvds_eep, + lvds_een, lvds_edp, lvds_edn, lvds_ecp, lvds_ecn, lvds_ebp, + lvds_ebn, lvds_eap, lvds_ean, lcd0_d18, lcd0_d17, dsi_dp3, + dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, dsi_cn, dsi_dp0, dsi_dn0, + dsi_dp2, dsi_dn2, sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0, + sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk, + spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx, + uart0_tx, i2c0_sclk, i2c0_sdata, sensor0_pclk, + sensor0_ckout, dnand_ale, dnand_cle, dnand_ceb0, dnand_ceb1, + dnand_ceb2, dnand_ceb3, uart2_rx, uart2_tx, uart2_rtsb, + uart2_ctsb, uart3_rx, uart3_tx, uart3_rtsb, uart3_ctsb, + pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, i2c1_sclk, + i2c1_sdata, i2c2_sclk, i2c2_sdata, csi_dn0, csi_dp0, + csi_dn1, csi_dp1, csi_dn2, csi_dp2, csi_dn3, csi_dp3, + csi_cn, csi_cp, dnand_d0, dnand_d1, dnand_d2, dnand_d3, + dnand_d4, dnand_d5, dnand_d6, dnand_d7, dnand_rb, dnand_rdb, + dnand_rdbn, dnand_wrb, porb, clko_25m, bsel, pkg0, pkg1, + pkg2, pkg3] + minItems: 1 + maxItems: 64 + + bias-pull-up: true + bias-pull-down: true + + drive-strength: + description: + Selects the drive strength for the specified pins, in mA. + enum: [2, 4, 8, 12] + + input-schmitt-enable: true + input-schmitt-disable: true + + additionalProperties: false + + additionalProperties: false + +required: + - compatible + - reg + - clocks + - gpio-controller + - gpio-ranges + - '#gpio-cells' + - interrupt-controller + - '#interrupt-cells' + - interrupts + +additionalProperties: false + +examples: + - | + #include + pinctrl: pinctrl@b01b0000 { + compatible = "actions,s500-pinctrl"; + reg = <0xb01b0000 0x40>, <0xb01b0040 0x10>, + <0xb01b0060 0x18>, <0xb01b0080 0xc>; + clocks = <&cmu 55>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 132>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + , + , + ; + + mmc0_pins: mmc0-pins { + pinmux { + groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp", + "sd0_cmd_mfp", "sd0_clk_mfp"; + function = "sd0"; + }; + + drv-pinconf { + groups = "sd0_d0_d3_drv", "sd0_cmd_drv", "sd0_clk_drv"; + drive-strength = <8>; + }; + + bias-pinconf { + pins = "sd0_d0", "sd0_d1", "sd0_d2", + "sd0_d3", "sd0_cmd"; + bias-pull-up; + }; + }; + }; + +... -- cgit v1.2.3-59-g8ed1b From d2f2f1321c194479c32ac13843a9299568da9304 Mon Sep 17 00:00:00 2001 From: Zhiyong Tao Date: Mon, 17 Aug 2020 08:17:01 +0800 Subject: dt-bindings: pinctrl: mt8192: add binding document The commit adds mt8192 compatible node in binding document. Signed-off-by: Zhiyong Tao Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20200817001702.1646-3-zhiyong.tao@mediatek.com Signed-off-by: Linus Walleij --- .../bindings/pinctrl/pinctrl-mt8192.yaml | 155 +++++++++++++++++++++ 1 file changed, 155 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml new file mode 100644 index 000000000000..5556def6b99b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml @@ -0,0 +1,155 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8192.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT8192 Pin Controller + +maintainers: + - Sean Wang + +description: | + The Mediatek's Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt8192-pinctrl + + gpio-controller: true + + '#gpio-cells': + description: | + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below + mentioned gpio binding representation for description of particular cells. + const: 2 + + gpio-ranges: + description: gpio valid number range. + maxItems: 1 + + reg: + description: | + Physical address base for gpio base registers. There are 11 GPIO + physical address base in mt8192. + maxItems: 11 + + reg-names: + description: | + Gpio base register names. + maxItems: 11 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + description: The interrupt outputs to sysirq. + maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '^pins': + type: object + description: | + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and + input schmitt. + An example of using macro: + pincontroller { + /* GPIO0 set as multifunction GPIO0 */ + state_0_node_a { + pinmux = ; + }; + /* GPIO1 set as multifunction PWM */ + state_0_node_b { + pinmux = ; + }; + }; + $ref: "pinmux-node.yaml" + + properties: + pinmux: + description: | + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are defined + as macros in dt-bindings/pinctrl/-pinfunc.h directly. + + drive-strength: + description: | + It can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See + dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10/12/14/16mA in mt8192. + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + #include + pio: pinctrl@10005000 { + compatible = "mediatek,mt8192-pinctrl"; + reg = <0x10005000 0x1000>, + <0x11c20000 0x1000>, + <0x11d10000 0x1000>, + <0x11d30000 0x1000>, + <0x11d40000 0x1000>, + <0x11e20000 0x1000>, + <0x11e70000 0x1000>, + <0x11ea0000 0x1000>, + <0x11f20000 0x1000>, + <0x11f30000 0x1000>, + <0x1000b000 0x1000>; + reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", + "iocfg_bl", "iocfg_br", "iocfg_lm", + "iocfg_lb", "iocfg_rt", "iocfg_lt", + "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 220>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + + pins { + pinmux = ; + output-low; + }; + }; -- cgit v1.2.3-59-g8ed1b From 1825c1fe0057e1904f772574e16d9cbbcaf30f85 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 10 Sep 2020 05:43:29 +0900 Subject: pinctrl: Add DT bindings for Toshiba Visconti TMPV7700 SoC Add pinctrl bindings for Toshiba Visconti TMPV7700 SoC series. Signed-off-by: Nobuhiro Iwamatsu Reviewed-by: Punit Agrawal Link: https://lore.kernel.org/r/20200909204336.2558-2-nobuhiro1.iwamatsu@toshiba.co.jp Signed-off-by: Linus Walleij --- .../bindings/pinctrl/toshiba,visconti-pinctrl.yaml | 92 ++++++++++++++++++++++ 1 file changed, 92 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml new file mode 100644 index 000000000000..d0d1a01140ea --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/toshiba,visconti-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toshiba Visconti TMPV770x pin mux/config controller + +maintainers: + - Nobuhiro Iwamatsu + +description: + Toshiba's Visconti ARM SoC a pin mux/config controller. + +properties: + compatible: + enum: + - toshiba,tmpv7708-pinctrl + + reg: + maxItems: 1 + +required: + - compatible + - reg + +patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength. + $ref: "pinmux-node.yaml" + + properties: + function: + description: + Function to mux. + $ref: "/schemas/types.yaml#/definitions/string" + enum: [i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c8, + spi0, spi1, spi2, spi3, spi4, spi5, spi6, + uart0, uart1, uart2, uart3, pwm, pcmif_out, pcmif_in] + + groups: + description: + Name of the pin group to use for the functions. + $ref: "/schemas/types.yaml#/definitions/string" + enum: [i2c0_grp, i2c1_grp, i2c2_grp, i2c3_grp, i2c4_grp, + i2c5_grp, i2c6_grp, i2c7_grp, i2c8_grp, + spi0_grp, spi0_cs0_grp, spi0_cs1_grp, spi0_cs2_grp, + spi1_grp, spi2_grp, spi3_grp, spi4_grp, spi5_grp, spi6_grp, + uart0_grp, uart1_grp, uart2_grp, uart3_grp, + pwm0_gpio4_grp, pwm0_gpio8_grp, pwm0_gpio12_grp, + pwm0_gpio16_grp, pwm1_gpio5_grp, pwm1_gpio9_grp, + pwm1_gpio13_grp, pwm1_gpio17_grp, pwm2_gpio6_grp, + pwm2_gpio10_grp, pwm2_gpio14_grp, pwm2_gpio18_grp, + pwm3_gpio7_grp, pwm3_gpio11_grp, pwm3_gpio15_grp, + pwm3_gpio19_grp, pcmif_out_grp, pcmif_in_grp] + + drive-strength: + enum: [2, 4, 6, 8, 16, 24, 32] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + bias-pull-up: true + + bias-pull-down: true + + bias-disable: true + +additionalProperties: false + +examples: + # Pinmux controller node + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pmux: pmux@24190000 { + compatible = "toshiba,tmpv7708-pinctrl"; + reg = <0 0x24190000 0 0x10000>; + + spi0_pins: spi0-pins { + function = "spi0"; + groups = "spi0_grp"; + }; + }; + }; -- cgit v1.2.3-59-g8ed1b From 96bef667ddbb82e891ed15b7087d1ae0a7081115 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Fri, 24 Jul 2020 15:00:31 +0800 Subject: dt-bindings: pinctrl: sunxi: Get rid of continual nesting Rather than a continual nesting of 'else' clauses, just make each 'if' a new entry under 'allOf' and get rid of the else. Signed-off-by: Yangtao Li Reviewed-by: Rob Herring Acked-by: Maxime Ripard Link: https://lore.kernel.org/r/229e4870dab1b34797304c384e68c7d04196423b.1595572867.git.frank@allwinnertech.com Signed-off-by: Linus Walleij --- .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 124 +++++++++++---------- 1 file changed, 68 insertions(+), 56 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml index 7556be6e2754..35a26abb02e7 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml @@ -155,62 +155,74 @@ allOf: minItems: 5 maxItems: 5 - else: - if: - properties: - compatible: - enum: - - allwinner,sun6i-a31-pinctrl - - allwinner,sun6i-a31s-pinctrl - - allwinner,sun50i-h6-pinctrl - - then: - properties: - interrupts: - minItems: 4 - maxItems: 4 - - else: - if: - properties: - compatible: - enum: - - allwinner,sun8i-a23-pinctrl - - allwinner,sun8i-a83t-pinctrl - - allwinner,sun50i-a64-pinctrl - - allwinner,sun50i-h5-pinctrl - - allwinner,suniv-f1c100s-pinctrl - - then: - properties: - interrupts: - minItems: 3 - maxItems: 3 - - else: - if: - properties: - compatible: - enum: - - allwinner,sun6i-a31-r-pinctrl - - allwinner,sun8i-a33-pinctrl - - allwinner,sun8i-h3-pinctrl - - allwinner,sun8i-v3-pinctrl - - allwinner,sun8i-v3s-pinctrl - - allwinner,sun9i-a80-r-pinctrl - - allwinner,sun50i-h6-r-pinctrl - - then: - properties: - interrupts: - minItems: 2 - maxItems: 2 - - else: - properties: - interrupts: - minItems: 1 - maxItems: 1 + - if: + properties: + compatible: + enum: + - allwinner,sun6i-a31-pinctrl + - allwinner,sun6i-a31s-pinctrl + - allwinner,sun50i-h6-pinctrl + + then: + properties: + interrupts: + minItems: 4 + maxItems: 4 + + - if: + properties: + compatible: + enum: + - allwinner,sun8i-a23-pinctrl + - allwinner,sun8i-a83t-pinctrl + - allwinner,sun50i-a64-pinctrl + - allwinner,sun50i-h5-pinctrl + - allwinner,suniv-f1c100s-pinctrl + + then: + properties: + interrupts: + minItems: 3 + maxItems: 3 + + - if: + properties: + compatible: + enum: + - allwinner,sun6i-a31-r-pinctrl + - allwinner,sun8i-a33-pinctrl + - allwinner,sun8i-h3-pinctrl + - allwinner,sun8i-v3-pinctrl + - allwinner,sun8i-v3s-pinctrl + - allwinner,sun9i-a80-r-pinctrl + - allwinner,sun50i-h6-r-pinctrl + + then: + properties: + interrupts: + minItems: 2 + maxItems: 2 + + - if: + properties: + compatible: + enum: + - allwinner,sun4i-a10-pinctrl + - allwinner,sun5i-a10s-pinctrl + - allwinner,sun5i-a13-pinctrl + - allwinner,sun7i-a20-pinctrl + - allwinner,sun8i-a23-r-pinctrl + - allwinner,sun8i-a83t-r-pinctrl + - allwinner,sun8i-h3-r-pinctrl + - allwinner,sun8i-r40-pinctrl + - allwinner,sun50i-a64-r-pinctrl + - nextthing,gr8-pinctrl + + then: + properties: + interrupts: + minItems: 1 + maxItems: 1 additionalProperties: false -- cgit v1.2.3-59-g8ed1b From 5e842dc23cd3a99051f615161bb0972b8dc10d66 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Fri, 24 Jul 2020 15:02:42 +0800 Subject: dt-bindings: pinctrl: sunxi: Add A100 pinctrl bindings Add device tree binding Documentation details for A100 pinctrl driver, which has a r pin controller and a pin controller with more irq lines. Signed-off-by: Yangtao Li Reviewed-by: Rob Herring Acked-by: Maxime Ripard Link: https://lore.kernel.org/r/a5773d677bcc89af3810cdd187fae54eced82f27.1595572867.git.frank@allwinnertech.com Signed-off-by: Linus Walleij --- .../bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml index 35a26abb02e7..34a17d5c6135 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml @@ -48,6 +48,8 @@ properties: - allwinner,sun9i-a80-r-pinctrl - allwinner,sun50i-a64-pinctrl - allwinner,sun50i-a64-r-pinctrl + - allwinner,sun50i-a100-pinctrl + - allwinner,sun50i-a100-r-pinctrl - allwinner,sun50i-h5-pinctrl - allwinner,sun50i-h6-pinctrl - allwinner,sun50i-h6-r-pinctrl @@ -143,6 +145,18 @@ allOf: # boards are defining it at the moment so it would generate a lot of # warnings. + - if: + properties: + compatible: + enum: + - allwinner,sun50i-a100-pinctrl + + then: + properties: + interrupts: + minItems: 7 + maxItems: 7 + - if: properties: compatible: @@ -216,6 +230,7 @@ allOf: - allwinner,sun8i-h3-r-pinctrl - allwinner,sun8i-r40-pinctrl - allwinner,sun50i-a64-r-pinctrl + - allwinner,sun50i-a100-r-pinctrl - nextthing,gr8-pinctrl then: -- cgit v1.2.3-59-g8ed1b From 7b9ec811752c17c4c6e70d296ef8aa205a7acacd Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 21 Aug 2020 13:22:08 +0200 Subject: dt-bindings: pinctrl: sh-pfc: Convert to json-schema Convert the Renesas Pin Function Controller (PFC) Device Tree binding documentation to json-schema. Document missing properties. Drop deprecated and obsolete #gpio-range-cells property. Update the example to match reality. Drop consumer examples, as they do not belong here. Signed-off-by: Geert Uytterhoeven Reviewed-by: Rob Herring Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20200821112208.5295-1-geert+renesas@glider.be --- .../bindings/pinctrl/renesas,pfc-pinctrl.txt | 188 -------------------- .../devicetree/bindings/pinctrl/renesas,pfc.yaml | 193 +++++++++++++++++++++ 2 files changed, 193 insertions(+), 188 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt deleted file mode 100644 index d75476e24514..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +++ /dev/null @@ -1,188 +0,0 @@ -* Renesas Pin Function Controller (GPIO and Pin Mux/Config) - -The Pin Function Controller (PFC) is a Pin Mux/Config controller. On SH73A0, -R8A73A4 and R8A7740 it also acts as a GPIO controller. - - -Pin Control ------------ - -Required Properties: - - - compatible: should be one of the following. - - "renesas,pfc-emev2": for EMEV2 (EMMA Mobile EV2) compatible pin-controller. - - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller. - - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller. - - "renesas,pfc-r8a7742": for R8A7742 (RZ/G1H) compatible pin-controller. - - "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller. - - "renesas,pfc-r8a7744": for R8A7744 (RZ/G1N) compatible pin-controller. - - "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller. - - "renesas,pfc-r8a77470": for R8A77470 (RZ/G1C) compatible pin-controller. - - "renesas,pfc-r8a774a1": for R8A774A1 (RZ/G2M) compatible pin-controller. - - "renesas,pfc-r8a774b1": for R8A774B1 (RZ/G2N) compatible pin-controller. - - "renesas,pfc-r8a774c0": for R8A774C0 (RZ/G2E) compatible pin-controller. - - "renesas,pfc-r8a774e1": for R8A774E1 (RZ/G2H) compatible pin-controller. - - "renesas,pfc-r8a7778": for R8A7778 (R-Car M1) compatible pin-controller. - - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller. - - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller. - - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller. - - "renesas,pfc-r8a7792": for R8A7792 (R-Car V2H) compatible pin-controller. - - "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller. - - "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller. - - "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller. - - "renesas,pfc-r8a7796": for R8A77960 (R-Car M3-W) compatible pin-controller. - - "renesas,pfc-r8a77961": for R8A77961 (R-Car M3-W+) compatible pin-controller. - - "renesas,pfc-r8a77965": for R8A77965 (R-Car M3-N) compatible pin-controller. - - "renesas,pfc-r8a77970": for R8A77970 (R-Car V3M) compatible pin-controller. - - "renesas,pfc-r8a77980": for R8A77980 (R-Car V3H) compatible pin-controller. - - "renesas,pfc-r8a77990": for R8A77990 (R-Car E3) compatible pin-controller. - - "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller. - - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller. - - - reg: Base address and length of each memory resource used by the pin - controller hardware module. - -Optional properties: - - - #gpio-range-cells: Mandatory when the PFC doesn't handle GPIO, forbidden - otherwise. Should be 3. - - - interrupts-extended: Specify the interrupts associated with external - IRQ pins. This property is mandatory when the PFC handles GPIOs and - forbidden otherwise. When specified, it must contain one interrupt per - external IRQ, sorted by external IRQ number. - -The PFC node also acts as a container for pin configuration nodes. Please refer -to pinctrl-bindings.txt in this directory for the definition of the term "pin -configuration node" and for the common pinctrl bindings used by client devices. - -Each pin configuration node represents a desired configuration for a pin, a -pin group, or a list of pins or pin groups. The configuration can include the -function to select on those pin(s) and pin configuration parameters (such as -pull-up and pull-down). - -Pin configuration nodes contain pin configuration properties, either directly -or grouped in child subnodes. Both pin muxing and configuration parameters can -be grouped in that way and referenced as a single pin configuration node by -client devices. - -A configuration node or subnode must reference at least one pin (through the -pins or pin groups properties) and contain at least a function or one -configuration parameter. When the function is present only pin groups can be -used to reference pins. - -All pin configuration nodes and subnodes names are ignored. All of those nodes -are parsed through phandles and processed purely based on their content. - -Pin Configuration Node Properties: - -- pins : An array of strings, each string containing the name of a pin. -- groups : An array of strings, each string containing the name of a pin - group. - -- function: A string containing the name of the function to mux to the pin - group(s) specified by the groups property. - - Valid values for pin, group and function names can be found in the group and - function arrays of the PFC data file corresponding to the SoC - (drivers/pinctrl/sh-pfc/pfc-*.c) - -The pin configuration parameters use the generic pinconf bindings defined in -pinctrl-bindings.txt in this directory. The supported parameters are -bias-disable, bias-pull-up, bias-pull-down, drive-strength and power-source. For -pins that have a configurable I/O voltage, the power-source value should be the -nominal I/O voltage in millivolts. - - -GPIO ----- - -On SH73A0, R8A73A4 and R8A7740 the PFC node is also a GPIO controller node. - -Required Properties: - - - gpio-controller: Marks the device node as a gpio controller. - - - #gpio-cells: Should be 2. The first cell is the GPIO number and the second - cell specifies GPIO flags, as defined in . Only the - GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported. - -The syntax of the gpio specifier used by client nodes should be the following -with values derived from the SoC user manual. - - <[phandle of the gpio controller node] - [pin number within the gpio controller] - [flags]> - -On other mach-shmobile platforms GPIO is handled by the gpio-rcar driver. -Please refer to Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml -for documentation of the GPIO device tree bindings on those platforms. - - -Examples --------- - -Example 1: SH73A0 (SH-Mobile AG5) pin controller node - - pfc: pin-controller@e6050000 { - compatible = "renesas,pfc-sh73a0"; - reg = <0xe6050000 0x8000>, - <0xe605801c 0x1c>; - gpio-controller; - #gpio-cells = <2>; - interrupts-extended = - <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, - <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, - <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, - <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, - <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, - <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, - <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, - <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; - }; - -Example 2: A GPIO LED node that references a GPIO - - #include - - leds { - compatible = "gpio-leds"; - led1 { - gpios = <&pfc 20 GPIO_ACTIVE_LOW>; - }; - }; - -Example 3: KZM-A9-GT (SH-Mobile AG5) default pin state hog and pin control maps - for the MMCIF and SCIFA4 devices - - &pfc { - pinctrl-0 = <&scifa4_pins>; - pinctrl-names = "default"; - - mmcif_pins: mmcif { - mux { - groups = "mmc0_data8_0", "mmc0_ctrl_0"; - function = "mmc0"; - }; - cfg { - groups = "mmc0_data8_0"; - pins = "PORT279"; - bias-pull-up; - }; - }; - - scifa4_pins: scifa4 { - groups = "scifa4_data", "scifa4_ctrl"; - function = "scifa4"; - }; - }; - -Example 4: KZM-A9-GT (SH-Mobile AG5) default pin state for the MMCIF device - - &mmcif { - pinctrl-0 = <&mmcif_pins>; - pinctrl-names = "default"; - - bus-width = <8>; - vmmc-supply = <®_1p8v>; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml new file mode 100644 index 000000000000..4efe117550bd --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml @@ -0,0 +1,193 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/renesas,pfc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Pin Function Controller (GPIO and Pin Mux/Config) + +maintainers: + - Geert Uytterhoeven + +description: + The Pin Function Controller (PFC) is a Pin Mux/Config controller. + On SH/R-Mobile SoCs it also acts as a GPIO controller. + +properties: + compatible: + enum: + - renesas,pfc-emev2 # EMMA Mobile EV2 + - renesas,pfc-r8a73a4 # R-Mobile APE6 + - renesas,pfc-r8a7740 # R-Mobile A1 + - renesas,pfc-r8a7742 # RZ/G1H + - renesas,pfc-r8a7743 # RZ/G1M + - renesas,pfc-r8a7744 # RZ/G1N + - renesas,pfc-r8a7745 # RZ/G1E + - renesas,pfc-r8a77470 # RZ/G1C + - renesas,pfc-r8a774a1 # RZ/G2M + - renesas,pfc-r8a774b1 # RZ/G2N + - renesas,pfc-r8a774c0 # RZ/G2E + - renesas,pfc-r8a774e1 # RZ/G2H + - renesas,pfc-r8a7778 # R-Car M1 + - renesas,pfc-r8a7779 # R-Car H1 + - renesas,pfc-r8a7790 # R-Car H2 + - renesas,pfc-r8a7791 # R-Car M2-W + - renesas,pfc-r8a7792 # R-Car V2H + - renesas,pfc-r8a7793 # R-Car M2-N + - renesas,pfc-r8a7794 # R-Car E2 + - renesas,pfc-r8a7795 # R-Car H3 + - renesas,pfc-r8a7796 # R-Car M3-W + - renesas,pfc-r8a77961 # R-Car M3-W+ + - renesas,pfc-r8a77965 # R-Car M3-N + - renesas,pfc-r8a77970 # R-Car V3M + - renesas,pfc-r8a77980 # R-Car V3H + - renesas,pfc-r8a77990 # R-Car E3 + - renesas,pfc-r8a77995 # R-Car D3 + - renesas,pfc-sh73a0 # SH-Mobile AG5 + + reg: + minItems: 1 + maxItems: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + minItems: 1 + maxItems: 16 + + interrupts-extended: + minItems: 32 + maxItems: 64 + description: + Specify the interrupts associated with external IRQ pins on SoCs where + the PFC acts as a GPIO controller. It must contain one interrupt per + external IRQ, sorted by external IRQ number. + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + +if: + properties: + compatible: + items: + enum: + - renesas,pfc-r8a73a4 + - renesas,pfc-r8a7740 + - renesas,pfc-sh73a0 +then: + required: + - interrupts-extended + - gpio-controller + - '#gpio-cells' + - gpio-ranges + - power-domains + +additionalProperties: + anyOf: + - type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + description: + Pin controller client devices use pin configuration subnodes (children + and grandchildren) for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + phandle: true + function: true + groups: true + pins: true + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: + enum: [ 3, 6, 9, 12, 15, 18, 21, 24 ] # Superset of supported values + power-source: + enum: [ 1800, 3300 ] + gpio-hog: true + gpios: true + input: true + output-high: true + output-low: true + + additionalProperties: false + + - type: object + properties: + phandle: true + + additionalProperties: + $ref: "#/additionalProperties/anyOf/0" + +examples: + - | + pfc: pinctrl@e6050000 { + compatible = "renesas,pfc-r8a7740"; + reg = <0xe6050000 0x8000>, + <0xe605800c 0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 0 212>; + interrupts-extended = + <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, + <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, + <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, + <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, + <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, + <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, + <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, + <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; + power-domains = <&pd_c5>; + + lcd0_mux { + /* DBGMD/LCDC0/FSIA MUX */ + gpio-hog; + gpios = <176 0>; + output-high; + }; + }; + + - | + pinctrl@e6060000 { + compatible = "renesas,pfc-r8a7795"; + reg = <0xe6060000 0x50c>; + + avb_pins: avb { + mux { + groups = "avb_link", "avb_mdio", "avb_mii"; + function = "avb"; + }; + + pins_mdio { + groups = "avb_mdio"; + drive-strength = <24>; + }; + + pins_mii_tx { + pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", + "PIN_AVB_TD0", "PIN_AVB_TD1", "PIN_AVB_TD2", + "PIN_AVB_TD3"; + drive-strength = <12>; + }; + }; + + keys_pins: keys { + pins = "GP_5_17", "GP_5_20", "GP_5_22", "GP_2_1"; + bias-pull-up; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + }; -- cgit v1.2.3-59-g8ed1b From a4eb6afa7c2c3795ec693cd806fd69593c9ecca7 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 21 Aug 2020 13:14:01 +0200 Subject: pinctrl: rza1: Switch to using "output-enable" For pins requiring software driven IO output operations, the RZ/A1 Pin Controller uses either the "output-high" or "output-low" DT property to enable the corresponding output buffer. The actual line value doesn't matter, as it is ignored. Commit 425562429d4f3b13 ("pinctrl: generic: Add output-enable property") introduced a new DT property for this specific use case. Update the RZ/A1 Pin Controller DT bindings and driver to use this new property instead. Preserve backwards compatibility with old DTBs in the driver, as this comes at a very small cost. Notes: - The DT binding examples already used the new property, - There are no upstream users of the old properties. Signed-off-by: Geert Uytterhoeven Reviewed-by: Chris Brandt Acked-by: Jacopo Mondi Acked-by: Rob Herring Link: https://lore.kernel.org/r/20200821111401.4021-1-geert+renesas@glider.be --- Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt | 5 ++--- drivers/pinctrl/sh-pfc/pinctrl-rza1.c | 3 ++- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt index fd3696eb36bf..38cdd23d3498 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt @@ -117,10 +117,9 @@ function or a GPIO controller alternatively. - input-enable: enable input bufer for pins requiring software driven IO input operations. - - output-high: + - output-enable: enable output buffer for pins requiring software driven IO output - operations. output-low can be used alternatively, as line value is - ignored by the driver. + operations. The hardware reference manual specifies when a pin has to be configured to work in bi-directional mode and when the IO direction has to be specified diff --git a/drivers/pinctrl/sh-pfc/pinctrl-rza1.c b/drivers/pinctrl/sh-pfc/pinctrl-rza1.c index a0cb586a46b7..15dd007700c2 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl-rza1.c +++ b/drivers/pinctrl/sh-pfc/pinctrl-rza1.c @@ -928,7 +928,8 @@ static int rza1_parse_pinmux_node(struct rza1_pinctrl *rza1_pctl, case PIN_CONFIG_INPUT_ENABLE: pinmux_flags |= MUX_FLAGS_SWIO_INPUT; break; - case PIN_CONFIG_OUTPUT: + case PIN_CONFIG_OUTPUT: /* for DT backwards compatibility */ + case PIN_CONFIG_OUTPUT_ENABLE: pinmux_flags |= MUX_FLAGS_SWIO_OUTPUT; default: break; -- cgit v1.2.3-59-g8ed1b From d4691b7f6231a022f20028ea27b6c49466b2acd6 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 21 Aug 2020 13:11:27 +0200 Subject: dt-bindings: pinctrl: renesas,rza2-pinctrl: Fix pin controller node name According to Devicetree Specification v0.2 and later, Section "Generic Names Recommendation", the node name for a pin controller device node should be "pinctrl". Signed-off-by: Geert Uytterhoeven Acked-by: Rob Herring Link: https://lore.kernel.org/r/20200821111127.3771-1-geert+renesas@glider.be --- Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml index b7911a994f3a..ce1f7343788f 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml @@ -84,7 +84,7 @@ additionalProperties: false examples: - | #include - pinctrl: pin-controller@fcffe000 { + pinctrl: pinctrl@fcffe000 { compatible = "renesas,r7s9210-pinctrl"; reg = <0xfcffe000 0x1000>; -- cgit v1.2.3-59-g8ed1b From 5398b2fa464722a3bb3cf4c264a19ac765974d98 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 21 Aug 2020 13:19:56 +0200 Subject: dt-bindings: pinctrl: rza1: Convert to json-schema Convert the Renesas RZ/A1 combined Pin and GPIO controller Device Tree binding documentation to json-schema. Rename "rza1-pinctrl" to "rza1-ports", to match the compatible value scheme. Use "pinctrl" generic node name. Drop generic and consumer examples, as they do not belong here. Signed-off-by: Geert Uytterhoeven Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20200821111956.4989-1-geert+renesas@glider.be --- .../bindings/pinctrl/renesas,rza1-pinctrl.txt | 222 --------------------- .../bindings/pinctrl/renesas,rza1-ports.yaml | 190 ++++++++++++++++++ 2 files changed, 190 insertions(+), 222 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt deleted file mode 100644 index 38cdd23d3498..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt +++ /dev/null @@ -1,222 +0,0 @@ -Renesas RZ/A1 combined Pin and GPIO controller - -The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO controller, -named "Ports" in the hardware reference manual. -Pin multiplexing and GPIO configuration is performed on a per-pin basis -writing configuration values to per-port register sets. -Each "port" features up to 16 pins, each of them configurable for GPIO -function (port mode) or in alternate function mode. -Up to 8 different alternate function modes exist for each single pin. - -Pin controller node -------------------- - -Required properties: - - compatible: should be: - - "renesas,r7s72100-ports": for RZ/A1H - - "renesas,r7s72101-ports", "renesas,r7s72100-ports": for RZ/A1M - - "renesas,r7s72102-ports": for RZ/A1L - - - reg - address base and length of the memory area where the pin controller - hardware is mapped to. - -Example: -Pin controller node for RZ/A1H SoC (r7s72100) - -pinctrl: pin-controller@fcfe3000 { - compatible = "renesas,r7s72100-ports"; - - reg = <0xfcfe3000 0x4230>; -}; - -Sub-nodes ---------- - -The child nodes of the pin controller node describe a pin multiplexing -function or a GPIO controller alternatively. - -- Pin multiplexing sub-nodes: - A pin multiplexing sub-node describes how to configure a set of - (or a single) pin in some desired alternate function mode. - A single sub-node may define several pin configurations. - A few alternate function require special pin configuration flags to be - supplied along with the alternate function configuration number. - The hardware reference manual specifies when a pin function requires - "software IO driven" mode to be specified. To do so use the generic - properties from the header file - to instruct the pin controller to perform the desired pin configuration - operation. - Please refer to pinctrl-bindings.txt to get to know more on generic - pin properties usage. - - The allowed generic formats for a pin multiplexing sub-node are the - following ones: - - node-1 { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - - node-2 { - sub-node-1 { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - - sub-node-2 { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - - ... - - sub-node-n { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - }; - - Use the second format when pins part of the same logical group need to have - different generic pin configuration flags applied. - - Client sub-nodes shall refer to pin multiplexing sub-nodes using the phandle - of the most external one. - - Eg. - - client-1 { - ... - pinctrl-0 = <&node-1>; - ... - }; - - client-2 { - ... - pinctrl-0 = <&node-2>; - ... - }; - - Required properties: - - pinmux: - integer array representing pin number and pin multiplexing configuration. - When a pin has to be configured in alternate function mode, use this - property to identify the pin by its global index, and provide its - alternate function configuration number along with it. - When multiple pins are required to be configured as part of the same - alternate function they shall be specified as members of the same - argument list of a single "pinmux" property. - Helper macros to ease assembling the pin index from its position - (port where it sits on and pin number) and alternate function identifier - are provided by the pin controller header file at: - - Integers values in "pinmux" argument list are assembled as: - ((PORT * 16 + PIN) | MUX_FUNC << 16) - - Optional generic properties: - - input-enable: - enable input bufer for pins requiring software driven IO input - operations. - - output-enable: - enable output buffer for pins requiring software driven IO output - operations. - - The hardware reference manual specifies when a pin has to be configured to - work in bi-directional mode and when the IO direction has to be specified - by software. Bi-directional pins are managed by the pin controller driver - internally, while software driven IO direction has to be explicitly - selected when multiple options are available. - - Example: - A serial communication interface with a TX output pin and an RX input pin. - - &pinctrl { - scif2_pins: serial2 { - pinmux = , ; - }; - }; - - Pin #0 on port #3 is configured as alternate function #6. - Pin #2 on port #3 is configured as alternate function #4. - - Example 2: - I2c master: both SDA and SCL pins need bi-directional operations - - &pinctrl { - i2c2_pins: i2c2 { - pinmux = , ; - }; - }; - - Pin #4 on port #1 is configured as alternate function #1. - Pin #5 on port #1 is configured as alternate function #1. - Both need to work in bi-directional mode, the driver manages this internally. - - Example 3: - Multi-function timer input and output compare pins. - Configure TIOC0A as software driven input and TIOC0B as software driven - output. - - &pinctrl { - tioc0_pins: tioc0 { - tioc0_input_pins { - pinumx = ; - input-enable; - }; - - tioc0_output_pins { - pinmux = ; - output-enable; - }; - }; - }; - - &tioc0 { - ... - pinctrl-0 = <&tioc0_pins>; - ... - }; - - Pin #0 on port #4 is configured as alternate function #2 with IO direction - specified by software as input. - Pin #1 on port #4 is configured as alternate function #1 with IO direction - specified by software as output. - -- GPIO controller sub-nodes: - Each port of the r7s72100 pin controller hardware is itself a GPIO controller. - Different SoCs have different numbers of available pins per port, but - generally speaking, each of them can be configured in GPIO ("port") mode - on this hardware. - Describe GPIO controllers using sub-nodes with the following properties. - - Required properties: - - gpio-controller - empty property as defined by the GPIO bindings documentation. - - #gpio-cells - number of cells required to identify and configure a GPIO. - Shall be 2. - - gpio-ranges - Describes a GPIO controller specifying its specific pin base, the pin - base in the global pin numbering space, and the number of controlled - pins, as defined by the GPIO bindings documentation. Refer to - Documentation/devicetree/bindings/gpio/gpio.txt file for a more detailed - description. - - Example: - A GPIO controller node, controlling 16 pins indexed from 0. - The GPIO controller base in the global pin indexing space is pin 48, thus - pins [0 - 15] on this controller map to pins [48 - 63] in the global pin - indexing space. - - port3: gpio-3 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 48 16>; - }; - - A device node willing to use pins controlled by this GPIO controller, shall - refer to it as follows: - - led1 { - gpios = <&port3 10 GPIO_ACTIVE_LOW>; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml new file mode 100644 index 000000000000..7f80578dc229 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml @@ -0,0 +1,190 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/A1 combined Pin and GPIO controller + +maintainers: + - Jacopo Mondi + - Geert Uytterhoeven + +description: + The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO + controller, named "Ports" in the hardware reference manual. + Pin multiplexing and GPIO configuration is performed on a per-pin basis + writing configuration values to per-port register sets. + Each "port" features up to 16 pins, each of them configurable for GPIO + function (port mode) or in alternate function mode. + Up to 8 different alternate function modes exist for each single pin. + +properties: + compatible: + oneOf: + - const: renesas,r7s72100-ports # RZ/A1H + - items: + - const: renesas,r7s72101-ports # RZ/A1M + - const: renesas,r7s72100-ports # fallback + - const: renesas,r7s72102-ports # RZ/A1L + + reg: + maxItems: 1 + +required: + - compatible + - reg + +patternProperties: + "^gpio-[0-9]*$": + type: object + + description: + Each port of the r7s72100 pin controller hardware is itself a GPIO + controller. + Different SoCs have different numbers of available pins per port, but + generally speaking, each of them can be configured in GPIO ("port") mode + on this hardware. + Describe GPIO controllers using sub-nodes with the following properties. + + properties: + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + maxItems: 1 + + required: + - gpio-controller + - '#gpio-cells' + - gpio-ranges + + +additionalProperties: + anyOf: + - type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + description: + A pin multiplexing sub-node describes how to configure a set of (or a + single) pin in some desired alternate function mode. + A single sub-node may define several pin configurations. + A few alternate function require special pin configuration flags to be + supplied along with the alternate function configuration number. + The hardware reference manual specifies when a pin function requires + "software IO driven" mode to be specified. To do so use the generic + properties from the header + file to instruct the pin controller to perform the desired pin + configuration operation. + The hardware reference manual specifies when a pin has to be configured + to work in bi-directional mode and when the IO direction has to be + specified by software. Bi-directional pins must be managed by the pin + controller driver internally, while software driven IO direction has to + be explicitly selected when multiple options are available. + + properties: + pinmux: + description: | + Integer array representing pin number and pin multiplexing + configuration. + When a pin has to be configured in alternate function mode, use + this property to identify the pin by its global index, and provide + its alternate function configuration number along with it. + When multiple pins are required to be configured as part of the + same alternate function they shall be specified as members of the + same argument list of a single "pinmux" property. + Helper macros to ease assembling the pin index from its position + (port where it sits on and pin number) and alternate function + identifier are provided by the pin controller header file at: + + Integers values in "pinmux" argument list are assembled as: + ((PORT * 16 + PIN) | MUX_FUNC << 16) + + phandle: true + input-enable: true + output-enable: true + + required: + - pinmux + + additionalProperties: false + + - type: object + properties: + phandle: true + + additionalProperties: + $ref: "#/additionalProperties/anyOf/0" + +examples: + - | + #include + pinctrl: pinctrl@fcfe3000 { + compatible = "renesas,r7s72100-ports"; + + reg = <0xfcfe3000 0x4230>; + + /* + * A GPIO controller node, controlling 16 pins indexed from 0. + * The GPIO controller base in the global pin indexing space is pin + * 48, thus pins [0 - 15] on this controller map to pins [48 - 63] + * in the global pin indexing space. + */ + port3: gpio-3 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + /* + * A serial communication interface with a TX output pin and an RX + * input pin. + * Pin #0 on port #3 is configured as alternate function #6. + * Pin #2 on port #3 is configured as alternate function #4. + */ + scif2_pins: serial2 { + pinmux = , ; + }; + + + /* + * I2c master: both SDA and SCL pins need bi-directional operations + * Pin #4 on port #1 is configured as alternate function #1. + * Pin #5 on port #1 is configured as alternate function #1. + * Both need to work in bi-directional mode, the driver must manage + * this internally. + */ + i2c2_pins: i2c2 { + pinmux = , ; + }; + + + /* + * Multi-function timer input and output compare pins. + */ + tioc0_pins: tioc0 { + /* + * Configure TIOC0A as software driven input + * Pin #0 on port #4 is configured as alternate function #2 + * with IO direction specified by software as input. + */ + tioc0_input_pins { + pinmux = ; + input-enable; + }; + + /* + * Configure TIOC0B as software driven output + * Pin #1 on port #4 is configured as alternate function #1 + * with IO direction specified by software as output. + */ + tioc0_output_pins { + pinmux = ; + output-enable; + }; + }; + }; -- cgit v1.2.3-59-g8ed1b From 5f76771a4a4514277f4618ba2fe20cb1d9ed5afd Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 21 Aug 2020 13:20:59 +0200 Subject: dt-bindings: pinctrl: rzn1: Convert to json-schema Convert the Renesas RZ/N1 Pin controller Device Tree binding documentation to json-schema. Use "pinctrl" generic node name. Drop generic and consumer examples, as they do not belong here. Signed-off-by: Geert Uytterhoeven Tested-by: Gareth Williams Reviewed-by: Gareth Williams Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20200821112059.5133-1-geert+renesas@glider.be --- .../bindings/pinctrl/renesas,rzn1-pinctrl.txt | 153 --------------------- .../bindings/pinctrl/renesas,rzn1-pinctrl.yaml | 129 +++++++++++++++++ 2 files changed, 129 insertions(+), 153 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.txt deleted file mode 100644 index 25e53acd523e..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.txt +++ /dev/null @@ -1,153 +0,0 @@ -Renesas RZ/N1 SoC Pinctrl node description. - -Pin controller node -------------------- -Required properties: -- compatible: SoC-specific compatible string "renesas,-pinctrl" - followed by "renesas,rzn1-pinctrl" as fallback. The SoC-specific compatible - strings must be one of: - "renesas,r9a06g032-pinctrl" for RZ/N1D - "renesas,r9a06g033-pinctrl" for RZ/N1S -- reg: Address base and length of the memory area where the pin controller - hardware is mapped to. -- clocks: phandle for the clock, see the description of clock-names below. -- clock-names: Contains the name of the clock: - "bus", the bus clock, sometimes described as pclk, for register accesses. - -Example: - pinctrl: pin-controller@40067000 { - compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl"; - reg = <0x40067000 0x1000>, <0x51000000 0x480>; - clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>; - clock-names = "bus"; - }; - -Sub-nodes ---------- - -The child nodes of the pin controller node describe a pin multiplexing -function. - -- Pin multiplexing sub-nodes: - A pin multiplexing sub-node describes how to configure a set of - (or a single) pin in some desired alternate function mode. - A single sub-node may define several pin configurations. - Please refer to pinctrl-bindings.txt to get to know more on generic - pin properties usage. - - The allowed generic formats for a pin multiplexing sub-node are the - following ones: - - node-1 { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - - node-2 { - sub-node-1 { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - - sub-node-2 { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - - ... - - sub-node-n { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - }; - - node-3 { - pinmux = , , ... ; - GENERIC_PINCONFIG; - - sub-node-1 { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - - ... - - sub-node-n { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - }; - - Use the latter two formats when pins part of the same logical group need to - have different generic pin configuration flags applied. Note that the generic - pinconfig in node-3 does not apply to the sub-nodes. - - Client sub-nodes shall refer to pin multiplexing sub-nodes using the phandle - of the most external one. - - Eg. - - client-1 { - ... - pinctrl-0 = <&node-1>; - ... - }; - - client-2 { - ... - pinctrl-0 = <&node-2>; - ... - }; - - Required properties: - - pinmux: - integer array representing pin number and pin multiplexing configuration. - When a pin has to be configured in alternate function mode, use this - property to identify the pin by its global index, and provide its - alternate function configuration number along with it. - When multiple pins are required to be configured as part of the same - alternate function they shall be specified as members of the same - argument list of a single "pinmux" property. - Integers values in the "pinmux" argument list are assembled as: - (PIN | MUX_FUNC << 8) - where PIN directly corresponds to the pl_gpio pin number and MUX_FUNC is - one of the alternate function identifiers defined in: - - These identifiers collapse the IO Multiplex Configuration Level 1 and - Level 2 numbers that are detailed in the hardware reference manual into a - single number. The identifiers for Level 2 are simply offset by 10. - Additional identifiers are provided to specify the MDIO source peripheral. - - Optional generic pinconf properties: - - bias-disable - disable any pin bias - - bias-pull-up - pull up the pin with 50 KOhm - - bias-pull-down - pull down the pin with 50 KOhm - - bias-high-impedance - high impedance mode - - drive-strength - sink or source at most 4, 6, 8 or 12 mA - - Example: - A serial communication interface with a TX output pin and an RX input pin. - - &pinctrl { - pins_uart0: pins_uart0 { - pinmux = < - RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */ - RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */ - >; - }; - }; - - Example 2: - Here we set the pull up on the RXD pin of the UART. - - &pinctrl { - pins_uart0: pins_uart0 { - pinmux = ; /* TXD */ - - pins_uart6_rx { - pinmux = ; /* RXD */ - bias-pull-up; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml new file mode 100644 index 000000000000..4a43af0d6e02 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/N1 Pin Controller + +maintainers: + - Gareth Williams + - Geert Uytterhoeven + +properties: + compatible: + items: + - enum: + - renesas,r9a06g032-pinctrl # RZ/N1D + - renesas,r9a06g033-pinctrl # RZ/N1S + - const: renesas,rzn1-pinctrl # Generic RZ/N1 + + reg: + items: + - description: GPIO Multiplexing Level1 Register Block + - description: GPIO Multiplexing Level2 Register Block + + clocks: + maxItems: 1 + + clock-names: + const: bus + description: + The bus clock, sometimes described as pclk, for register accesses. + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: + anyOf: + - type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + description: + A pin multiplexing sub-node describes how to configure a set of (or a + single) pin in some desired alternate function mode. + A single sub-node may define several pin configurations. + + properties: + pinmux: + description: | + Integer array representing pin number and pin multiplexing + configuration. + When a pin has to be configured in alternate function mode, use + this property to identify the pin by its global index, and provide + its alternate function configuration number along with it. + When multiple pins are required to be configured as part of the + same alternate function they shall be specified as members of the + same argument list of a single "pinmux" property. + Integers values in the "pinmux" argument list are assembled as: + (PIN | MUX_FUNC << 8) + where PIN directly corresponds to the pl_gpio pin number and + MUX_FUNC is one of the alternate function identifiers defined in: + + These identifiers collapse the IO Multiplex Configuration Level 1 + and Level 2 numbers that are detailed in the hardware reference + manual into a single number. The identifiers for Level 2 are simply + offset by 10. Additional identifiers are provided to specify the + MDIO source peripheral. + + phandle: true + bias-disable: true + bias-pull-up: + description: Pull up the pin with 50 kOhm + bias-pull-down: + description: Pull down the pin with 50 kOhm + bias-high-impedance: true + drive-strength: + enum: [ 4, 6, 8, 12 ] + + required: + - pinmux + + additionalProperties: + $ref: "#/additionalProperties/anyOf/0" + + - type: object + properties: + phandle: true + + additionalProperties: + $ref: "#/additionalProperties/anyOf/0" + +examples: + - | + #include + #include + pinctrl: pinctrl@40067000 { + compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl"; + reg = <0x40067000 0x1000>, <0x51000000 0x480>; + clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>; + clock-names = "bus"; + + /* + * A serial communication interface with a TX output pin and an RX + * input pin. + */ + pins_uart0: pins_uart0 { + pinmux = < + RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */ + RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */ + >; + }; + + /* + * Set the pull-up on the RXD pin of the UART. + */ + pins_uart0_alt: pins_uart0_alt { + pinmux = ; + + pins_uart6_rx { + pinmux = ; + bias-pull-up; + }; + }; + }; -- cgit v1.2.3-59-g8ed1b From 3c41f0609e63dbef49435263198cb8b5c5d9dede Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Mon, 7 Sep 2020 13:02:20 +0200 Subject: pinctrl: mt65xx: add OF bindings for MT8167 Add binding documentation of pinctrl-mt65xx for MT8167 SoC. Signed-off-by: Fabien Parent Acked-by: Rob Herring Link: https://lore.kernel.org/r/20200907110221.1691168-1-fparent@baylibre.com Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt index 205be98ae078..931a18cd1e23 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt @@ -10,6 +10,7 @@ Required properties: "mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl. "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl. "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl. + "mediatek,mt8167-pinctrl", compatible with mt8167 pinctrl. "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl. "mediatek,mt8516-pinctrl", compatible with mt8516 pinctrl. - pins-are-numbered: Specify the subnodes are using numbered pinmux to -- cgit v1.2.3-59-g8ed1b From cdfd8606e096a94265984efc247e938f8dad8034 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 28 Sep 2020 20:45:15 +0200 Subject: dt-bindings: pinctrl: renesas,pfc: align example GPIO hog name with dtschema The convention for node names is to use hyphens, not underscores. dtschema expects GPIO hogs to end with 'hog' suffix. Adjust the example DTS in the binding. No changes to binding itself. Reported-by: Rob Herring Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200928184515.7345-1-krzk@kernel.org Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml index 4efe117550bd..5b5b1b9d2ec7 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml @@ -148,7 +148,7 @@ examples: <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; power-domains = <&pd_c5>; - lcd0_mux { + lcd0-mux-hog { /* DBGMD/LCDC0/FSIA MUX */ gpio-hog; gpios = <176 0>; -- cgit v1.2.3-59-g8ed1b From 1e871d0c0bde1f7180c610d1f01f25250be20f7d Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Thu, 17 Sep 2020 16:12:56 +0300 Subject: dt-bindings: pinctrl: at91-pio4: add microchip,sama7g5 Add compatible string for microchip sama7g5 SoC. Signed-off-by: Eugen Hristev Reviewed-by: Nicolas Ferre Acked-by: Ludovic Desroches Acked-by: Rob Herring Link: https://lore.kernel.org/r/20200917131257.273882-1-eugen.hristev@microchip.com Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt index 04d16fb69eb7..265015bc0603 100644 --- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt @@ -4,7 +4,9 @@ The Atmel PIO4 controller is used to select the function of a pin and to configure it. Required properties: -- compatible: "atmel,sama5d2-pinctrl". +- compatible: + "atmel,sama5d2-pinctrl" + "microchip,sama7g5-pinctrl" - reg: base address and length of the PIO controller. - interrupts: interrupt outputs from the controller, one for each bank. - interrupt-controller: mark the device node as an interrupt controller. -- cgit v1.2.3-59-g8ed1b From 3163508b207f4622ba6f288127d68656a98e36a6 Mon Sep 17 00:00:00 2001 From: Drew Fustini Date: Sat, 19 Sep 2020 22:08:37 +0200 Subject: pinctrl: Document pinctrl-single,pins when #pinctrl-cells = 2 Document the values in pinctrl-single,pins when #pinctrl-cells = <2> Fixes: 27c90e5e48d0 ("ARM: dts: am33xx-l4: change #pinctrl-cells from 1 to 2") Reported-by: Trent Piepho Signed-off-by: Drew Fustini Reviewed-by: Rob Herring Acked-by: Tony Lindgren Link: https://lore.kernel.org/linux-omap/3139716.CMS8C0sQ7x@zen.local/ Link: https://lore.kernel.org/r/20200919200836.3218536-1-drew@beagleboard.org Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/pinctrl-single.txt | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt index e705acd3612c..f903eb4471f8 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt @@ -94,16 +94,23 @@ pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as specified in the pinctrl-bindings.txt document in this directory. The pin configuration nodes for pinctrl-single are specified as pinctrl -register offset and value pairs using pinctrl-single,pins. Only the bits -specified in pinctrl-single,function-mask are updated. For example, setting -a pin for a device could be done with: +register offset and values using pinctrl-single,pins. Only the bits specified +in pinctrl-single,function-mask are updated. + +When #pinctrl-cells = 1, then setting a pin for a device could be done with: pinctrl-single,pins = <0xdc 0x118>; -Where 0xdc is the offset from the pinctrl register base address for the -device pinctrl register, and 0x118 contains the desired value of the -pinctrl register. See the device example and static board pins example -below for more information. +Where 0xdc is the offset from the pinctrl register base address for the device +pinctrl register, and 0x118 contains the desired value of the pinctrl register. + +When #pinctrl-cells = 2, then setting a pin for a device could be done with: + + pinctrl-single,pins = <0xdc 0x30 0x07>; + +Where 0x30 is the pin configuration value and 0x07 is the pin mux mode value. +These two values are OR'd together to produce the value stored at offset 0xdc. +See the device example and static board pins example below for more information. In case when one register changes more than one pin's mux the pinctrl-single,bits need to be used which takes three parameters: -- cgit v1.2.3-59-g8ed1b From 4e787e0405342e9c21558ead99d39d1cdef1b388 Mon Sep 17 00:00:00 2001 From: Clément Péron Date: Mon, 5 Oct 2020 21:09:39 +0200 Subject: dt-bindings: pinctrl: sunxi: Allow pinctrl with more interrupt banks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Recently introduced Allwinner A100 pinctrl block has 7 interrupts. This trig a warning when running dtb_checks: sun50i-a100-allwinner-perf1.dt.yaml: pinctrl@300b000: interrupts: [...] is too long From schema: .../allwinner,sun4i-a10-pinctrl.yaml Fix this by allowing up to 7 interrupts. Signed-off-by: Clément Péron Acked-by: Rob Herring Link: https://lore.kernel.org/r/20201005190939.21016-1-peron.clem@gmail.com Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml index 34a17d5c6135..5240487dfe50 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml @@ -61,7 +61,7 @@ properties: interrupts: minItems: 1 - maxItems: 5 + maxItems: 7 description: One interrupt per external interrupt bank supported on the controller, sorted by bank number ascending order. -- cgit v1.2.3-59-g8ed1b