From 757a4b2913eb46df23af9e151e2cdd326d4542b5 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 15 Feb 2019 11:19:55 +0530 Subject: arm64: dts: hisilicon: hi3670: Add reset controller support Add reset controller support for HiSilicon HI3670 SoC. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 2ed06e4588b8..bc8363bc3b9c 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -151,6 +151,13 @@ #clock-cells = <1>; }; + crg_rst: crg_rst_controller { + compatible = "hisilicon,hi3670-reset", + "hisilicon,hi3660-reset"; + #reset-cells = <2>; + hisi,rst-syscon = <&crg_ctrl>; + }; + pctrl: pctrl@e8a09000 { compatible = "hisilicon,hi3670-pctrl", "syscon"; reg = <0x0 0xe8a09000 0x0 0x1000>; -- cgit v1.2.3-59-g8ed1b From 570274cdba34c01fb1e84db3648cb22b258cc394 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 28 Feb 2019 21:15:10 +0530 Subject: arm64: dts: hisilicon: hi3670: Add MMC controller support Add MMC controller support for HiSilicon HI3670 SoC reusing the HI3660 Designware MMC driver. There are 2 DWMMC controllers present in this SoC: 1. DWMMC1 is used for SD card (SD) 2. DWMMC2 is used for WiFi (SDIO) Signed-off-by: Manivannan Sadhasivam Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 37 +++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index bc8363bc3b9c..30177543cc8f 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -654,5 +654,42 @@ clocks = <&sctrl HI3670_PCLK_AO_GPIO6>; clock-names = "apb_pclk"; }; + + /* SD */ + dwmmc1: dwmmc1@ff37f000 { + compatible = "hisilicon,hi3670-dw-mshc", + "hisilicon,hi3660-dw-mshc"; + reg = <0x0 0xff37f000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&crg_ctrl HI3670_CLK_GATE_SD>, + <&crg_ctrl HI3670_HCLK_GATE_SD>; + clock-names = "ciu", "biu"; + clock-frequency = <3200000>; + resets = <&crg_rst 0x94 18>; + reset-names = "reset"; + hisilicon,peripheral-syscon = <&sctrl>; + card-detect-delay = <200>; + status = "disabled"; + }; + + /* SDIO */ + dwmmc2: dwmmc2@fc183000 { + compatible = "hisilicon,hi3670-dw-mshc", + "hisilicon,hi3660-dw-mshc"; + reg = <0x0 0xfc183000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&crg_ctrl HI3670_CLK_GATE_SDIO>, + <&crg_ctrl HI3670_HCLK_GATE_SDIO>; + clock-names = "ciu", "biu"; + clock-frequency = <3200000>; + resets = <&crg_rst 0x94 20>; + reset-names = "reset"; + card-detect-delay = <200>; + status = "disabled"; + }; }; }; -- cgit v1.2.3-59-g8ed1b From 1761101048a3144bf141359b15a6132c3d3cc001 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 28 Feb 2019 21:15:11 +0530 Subject: arm64: dts: hisilicon: hikey970: Add SD and WiFi support Add SD and WiFi support for HiKey970 board based on HI3670 SoC. Due to the absence of the PMIC driver, fixed regulators are sourced to make the driver working. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts | 75 ++++++++++++++ .../arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi | 115 +++++++++++++++++++++ 2 files changed, 190 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts index c9775b66629f..7dac33d4fd5c 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts @@ -8,6 +8,7 @@ */ /dts-v1/; +#include #include "hi3670.dtsi" #include "hikey970-pinctrl.dtsi" @@ -17,6 +18,8 @@ compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670"; aliases { + mshc1 = &dwmmc1; + mshc2 = &dwmmc2; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -35,6 +38,37 @@ /* expect bootloader to fill in this region */ reg = <0x0 0x0 0x0 0x0>; }; + + sd_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + sd_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + wlan_en: wlan-en-1-8v { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + /* GPIO_051_WIFI_EN */ + gpio = <&gpio6 3 0>; + + /* WLAN card specific delay */ + startup-delay-us = <70000>; + enable-active-high; + }; }; /* @@ -354,6 +388,47 @@ "GPIO_231_HDMI_INT"; }; +&dwmmc1 { + bus-width = <0x4>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + cap-sd-highspeed; + disable-wp; + cd-inverted; + cd-gpios = <&gpio25 5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sd_pmx_func + &sd_clk_cfg_func + &sd_cfg_func>; + vmmc-supply = <&sd_3v3>; + vqmmc-supply = <&sd_1v8>; + status = "okay"; +}; + +&dwmmc2 { /* WIFI */ + bus-width = <0x4>; + non-removable; + broken-cd; + cap-power-off-card; + pinctrl-names = "default"; + pinctrl-0 = <&sdio_pmx_func + &sdio_clk_cfg_func + &sdio_cfg_func>; + /* WL_EN */ + vmmc-supply = <&wlan_en>; + status = "ok"; + + wlcore: wlcore@2 { + compatible = "ti,wl1837"; + reg = <2>; /* sdio func num */ + /* WL_IRQ, GPIO_177_WL_WAKEUP_AP */ + interrupt-parent = <&gpio22>; + interrupts = <1 IRQ_TYPE_EDGE_RISING>; + }; +}; + &uart0 { /* On High speed expansion header */ label = "HS-UART0"; diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi index 67bb52d43619..d456b0aa6f58 100644 --- a/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi @@ -196,6 +196,16 @@ /* pin base, nr pins & gpio function */ pinctrl-single,gpio-range = <&range 0 10 0>; + sdio_pmx_func: sdio_pmx_func { + pinctrl-single,pins = < + 0x000 MUX_M1 /* SDIO_CLK */ + 0x004 MUX_M1 /* SDIO_CMD */ + 0x008 MUX_M1 /* SDIO_DATA0 */ + 0x00c MUX_M1 /* SDIO_DATA1 */ + 0x010 MUX_M1 /* SDIO_DATA2 */ + 0x014 MUX_M1 /* SDIO_DATA3 */ + >; + }; }; pmx6: pinmux@fc182800 { @@ -203,6 +213,52 @@ reg = <0x0 0xfc182800 0x0 0x028>; #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; + + sdio_clk_cfg_func: sdio_clk_cfg_func { + pinctrl-single,pins = < + 0x000 0x0 /* SDIO_CLK */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE6_32MA DRIVE6_MASK + >; + }; + + sdio_cfg_func: sdio_cfg_func { + pinctrl-single,pins = < + 0x004 0x0 /* SDIO_CMD */ + 0x008 0x0 /* SDIO_DATA0 */ + 0x00c 0x0 /* SDIO_DATA1 */ + 0x010 0x0 /* SDIO_DATA2 */ + 0x014 0x0 /* SDIO_DATA3 */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE6_19MA DRIVE6_MASK + >; + }; }; pmx7: pinmux@ff37e000 { @@ -214,6 +270,17 @@ pinctrl-single,function-mask = <7>; /* pin base, nr pins & gpio function */ pinctrl-single,gpio-range = <&range 0 12 0>; + + sd_pmx_func: sd_pmx_func { + pinctrl-single,pins = < + 0x000 MUX_M1 /* SD_CLK */ + 0x004 MUX_M1 /* SD_CMD */ + 0x008 MUX_M1 /* SD_DATA0 */ + 0x00c MUX_M1 /* SD_DATA1 */ + 0x010 MUX_M1 /* SD_DATA2 */ + 0x014 MUX_M1 /* SD_DATA3 */ + >; + }; }; pmx8: pinmux@ff37e800 { @@ -221,6 +288,54 @@ reg = <0x0 0xff37e800 0x0 0x030>; #pinctrl-cells = <1>; pinctrl-single,register-width = <0x20>; + + sd_clk_cfg_func: sd_clk_cfg_func { + pinctrl-single,pins = < + 0x000 0x0 /* SD_CLK */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE6_32MA + DRIVE6_MASK + >; + }; + + sd_cfg_func: sd_cfg_func { + pinctrl-single,pins = < + 0x004 0x0 /* SD_CMD */ + 0x008 0x0 /* SD_DATA0 */ + 0x00c 0x0 /* SD_DATA1 */ + 0x010 0x0 /* SD_DATA2 */ + 0x014 0x0 /* SD_DATA3 */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE6_19MA + DRIVE6_MASK + >; + }; }; pmx1: pinmux@fff11000 { -- cgit v1.2.3-59-g8ed1b From 792cea3f48add8ed13febab52a616cb52c3c7c7a Mon Sep 17 00:00:00 2001 From: John Stultz Date: Thu, 4 Apr 2019 01:16:26 -0700 Subject: arm64: dts: hi3660: Add dma to uart nodes Try to add DMA support to the uart nodes following the assignments made in the dts from the victoria vendor kernel here: https://consumer.huawei.com/en/opensource/detail/?siteCode=worldwide&keywords=p10&fileType=openSourceSoftware&pageSize=10&curPage=1 Cc: Tanglei Han Cc: Zhuangluan Su Cc: Ryan Grachek Cc: Manivannan Sadhasivam Cc: Wei Xu Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Acked-by: Manivannan Sadhasivam Signed-off-by: John Stultz Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 2f19e0e5b7cf..a3eeab1e1283 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -478,6 +478,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfdf00000 0x0 0x1000>; interrupts = ; + dma-names = "rx", "tx"; + dmas = <&dma0 2 &dma0 3>; clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, <&crg_ctrl HI3660_CLK_GATE_UART1>; clock-names = "uartclk", "apb_pclk"; @@ -490,6 +492,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfdf03000 0x0 0x1000>; interrupts = ; + dma-names = "rx", "tx"; + dmas = <&dma0 4 &dma0 5>; clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, <&crg_ctrl HI3660_PCLK>; clock-names = "uartclk", "apb_pclk"; @@ -514,6 +518,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfdf01000 0x0 0x1000>; interrupts = ; + dma-names = "rx", "tx"; + dmas = <&dma0 6 &dma0 7>; clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, <&crg_ctrl HI3660_CLK_GATE_UART4>; clock-names = "uartclk", "apb_pclk"; @@ -526,6 +532,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfdf05000 0x0 0x1000>; interrupts = ; + dma-names = "rx", "tx"; + dmas = <&dma0 8 &dma0 9>; clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, <&crg_ctrl HI3660_CLK_GATE_UART5>; clock-names = "uartclk", "apb_pclk"; -- cgit v1.2.3-59-g8ed1b From c9726326006535d95556b19aae524db6f8f8cc5e Mon Sep 17 00:00:00 2001 From: Youlin Wang Date: Thu, 4 Apr 2019 01:16:27 -0700 Subject: arm64: dts: hi3660: Add hisi asp dma device Add asp-dma device to hi3660 dts Cc: Tanglei Han Cc: Zhuangluan Su Cc: Ryan Grachek Cc: Manivannan Sadhasivam Cc: Wei Xu Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Acked-by: Manivannan Sadhasivam Signed-off-by: Youlin Wang Signed-off-by: Tanglei Han Signed-off-by: John Stultz Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index a3eeab1e1283..fb5498d177b9 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -567,6 +567,16 @@ dma-type = "hi3660_dma"; }; + asp_dmac: dma-controller@e804b000 { + compatible = "hisilicon,hisi-pcm-asp-dma-1.0"; + reg = <0x0 0xe804b000 0x0 0x1000>; + #dma-cells = <1>; + dma-channels = <16>; + dma-requests = <32>; + interrupts = ; + interrupt-names = "asp_dma_irq"; + }; + rtc0: rtc@fff04000 { compatible = "arm,pl031", "arm,primecell"; reg = <0x0 0Xfff04000 0x0 0x1000>; -- cgit v1.2.3-59-g8ed1b From 6d09e003db3dd71587705eb5ac6ad0a5578705f8 Mon Sep 17 00:00:00 2001 From: John Stultz Date: Thu, 4 Apr 2019 01:16:28 -0700 Subject: arm64: dts: hi3660: Fixup unofficial dma-min-chan to dma-channel-mask A undocumented and unimplemented binding got into the hi3660 dtsi, and this switches that binding to the now documented one. Cc: Tanglei Han Cc: Zhuangluan Su Cc: Ryan Grachek Cc: Manivannan Sadhasivam Cc: Wei Xu Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Signed-off-by: John Stultz Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index fb5498d177b9..aa6a8ad31be2 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -560,7 +560,7 @@ #dma-cells = <1>; dma-channels = <16>; dma-requests = <32>; - dma-min-chan = <1>; + dma-channel-mask = <0xfffe>; interrupts = ; clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>; dma-no-cci; -- cgit v1.2.3-59-g8ed1b From ddd0dc915647f12b5cbfa0a5e7d65389dcd71771 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Sat, 5 Jan 2019 12:58:58 +0530 Subject: arm64: dts: hisilicon: hi3670: Add UFS controller support Add UFS controller support for HiSilicon HI3670 SoC. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 30177543cc8f..2dcffa3ed218 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -655,6 +655,24 @@ clock-names = "apb_pclk"; }; + /* UFS */ + ufs: ufs@ff3c0000 { + compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1"; + /* 0: HCI standard */ + /* 1: UFS SYS CTRL */ + reg = <0x0 0xff3c0000 0x0 0x1000>, + <0x0 0xff3e0000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>, + <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>; + clock-names = "ref_clk", "phy_clk"; + freq-table-hz = <0 0>, <0 0>; + /* offset: 0x84; bit: 12 */ + resets = <&crg_rst 0x84 12>; + reset-names = "rst"; + }; + /* SD */ dwmmc1: dwmmc1@ff37f000 { compatible = "hisilicon,hi3670-dw-mshc", -- cgit v1.2.3-59-g8ed1b