From 60fb32ca61390360f2cce750ad2715b80e629027 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Tue, 17 Apr 2012 15:33:57 +1000 Subject: m68knommu: move the 527x platform code into the common ColdFire code directory All these separate directories for each ColdFire CPU SoC varient seems like overkill. The majority of them only contain a single small config file. Move these into the common ColdFire code directory. Signed-off-by: Greg Ungerer --- arch/m68k/Makefile | 1 - arch/m68k/platform/527x/Makefile | 18 ----- arch/m68k/platform/527x/config.c | 141 ----------------------------------- arch/m68k/platform/coldfire/Makefile | 2 +- arch/m68k/platform/coldfire/m527x.c | 141 +++++++++++++++++++++++++++++++++++ 5 files changed, 142 insertions(+), 161 deletions(-) delete mode 100644 arch/m68k/platform/527x/Makefile delete mode 100644 arch/m68k/platform/527x/config.c create mode 100644 arch/m68k/platform/coldfire/m527x.c (limited to 'arch/m68k') diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile index 2d7a4d987cf6..7e138d61e297 100644 --- a/arch/m68k/Makefile +++ b/arch/m68k/Makefile @@ -115,7 +115,6 @@ core-$(CONFIG_M68000) += arch/m68k/platform/68328/ core-$(CONFIG_M68EZ328) += arch/m68k/platform/68EZ328/ core-$(CONFIG_M68VZ328) += arch/m68k/platform/68VZ328/ core-$(CONFIG_COLDFIRE) += arch/m68k/platform/coldfire/ -core-$(CONFIG_M527x) += arch/m68k/platform/527x/ core-$(CONFIG_M528x) += arch/m68k/platform/528x/ core-$(CONFIG_M5307) += arch/m68k/platform/5307/ core-$(CONFIG_M532x) += arch/m68k/platform/532x/ diff --git a/arch/m68k/platform/527x/Makefile b/arch/m68k/platform/527x/Makefile deleted file mode 100644 index 8755c9e6c66b..000000000000 --- a/arch/m68k/platform/527x/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# Makefile for the linux kernel. -# - -# -# If you want to play with the HW breakpoints then you will -# need to add define this, which will give you a stack backtrace -# on the console port whenever a DBG interrupt occurs. You have to -# set up you HW breakpoints to trigger a DBG interrupt: -# -# ccflags-y := -DTRAP_DBG_INTERRUPT -# asflags-y := -DTRAP_DBG_INTERRUPT -# - -asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 - -obj-y := config.o - diff --git a/arch/m68k/platform/527x/config.c b/arch/m68k/platform/527x/config.c deleted file mode 100644 index 9b0b66aabd1b..000000000000 --- a/arch/m68k/platform/527x/config.c +++ /dev/null @@ -1,141 +0,0 @@ -/***************************************************************************/ - -/* - * linux/arch/m68knommu/platform/527x/config.c - * - * Sub-architcture dependent initialization code for the Freescale - * 5270/5271 CPUs. - * - * Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com) - * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com) - */ - -/***************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/***************************************************************************/ - -struct mcf_gpio_chip mcf_gpio_chips[] = { -#if defined(CONFIG_M5271) - MCFGPS(PIRQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR), - MCFGPF(ADDR, 13, 3), - MCFGPF(DATAH, 16, 8), - MCFGPF(DATAL, 24, 8), - MCFGPF(BUSCTL, 32, 8), - MCFGPF(BS, 40, 4), - MCFGPF(CS, 49, 7), - MCFGPF(SDRAM, 56, 6), - MCFGPF(FECI2C, 64, 4), - MCFGPF(UARTH, 72, 2), - MCFGPF(UARTL, 80, 8), - MCFGPF(QSPI, 88, 5), - MCFGPF(TIMER, 96, 8), -#elif defined(CONFIG_M5275) - MCFGPS(PIRQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR), - MCFGPF(BUSCTL, 8, 8), - MCFGPF(ADDR, 21, 3), - MCFGPF(CS, 25, 7), - MCFGPF(FEC0H, 32, 8), - MCFGPF(FEC0L, 40, 8), - MCFGPF(FECI2C, 48, 6), - MCFGPF(QSPI, 56, 7), - MCFGPF(SDRAM, 64, 8), - MCFGPF(TIMERH, 72, 4), - MCFGPF(TIMERL, 80, 4), - MCFGPF(UARTL, 88, 8), - MCFGPF(FEC1H, 96, 8), - MCFGPF(FEC1L, 104, 8), - MCFGPF(BS, 114, 2), - MCFGPF(IRQ, 121, 7), - MCFGPF(USBH, 128, 1), - MCFGPF(USBL, 136, 8), - MCFGPF(UARTH, 144, 4), -#endif -}; - -unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); - -/***************************************************************************/ - -#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) - -static void __init m527x_qspi_init(void) -{ -#if defined(CONFIG_M5271) - u16 par; - - /* setup QSPS pins for QSPI with gpio CS control */ - writeb(0x1f, MCFGPIO_PAR_QSPI); - /* and CS2 & CS3 as gpio */ - par = readw(MCFGPIO_PAR_TIMER); - par &= 0x3f3f; - writew(par, MCFGPIO_PAR_TIMER); -#elif defined(CONFIG_M5275) - /* setup QSPS pins for QSPI with gpio CS control */ - writew(0x003e, MCFGPIO_PAR_QSPI); -#endif -} - -#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ - -/***************************************************************************/ - -static void __init m527x_uarts_init(void) -{ - u16 sepmask; - - /* - * External Pin Mask Setting & Enable External Pin for Interface - */ - sepmask = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART); - sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK; - writew(sepmask, MCF_IPSBAR + MCF_GPIO_PAR_UART); -} - -/***************************************************************************/ - -static void __init m527x_fec_init(void) -{ - u16 par; - u8 v; - - /* Set multi-function pins to ethernet mode for fec0 */ -#if defined(CONFIG_M5271) - v = readb(MCF_IPSBAR + 0x100047); - writeb(v | 0xf0, MCF_IPSBAR + 0x100047); -#else - par = readw(MCF_IPSBAR + 0x100082); - writew(par | 0xf00, MCF_IPSBAR + 0x100082); - v = readb(MCF_IPSBAR + 0x100078); - writeb(v | 0xc0, MCF_IPSBAR + 0x100078); - - /* Set multi-function pins to ethernet mode for fec1 */ - par = readw(MCF_IPSBAR + 0x100082); - writew(par | 0xa0, MCF_IPSBAR + 0x100082); - v = readb(MCF_IPSBAR + 0x100079); - writeb(v | 0xc0, MCF_IPSBAR + 0x100079); -#endif -} - -/***************************************************************************/ - -void __init config_BSP(char *commandp, int size) -{ - mach_sched_init = hw_timer_init; - m527x_uarts_init(); - m527x_fec_init(); -#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) - m527x_qspi_init(); -#endif -} - -/***************************************************************************/ diff --git a/arch/m68k/platform/coldfire/Makefile b/arch/m68k/platform/coldfire/Makefile index ec81d0545592..8bef3463de21 100644 --- a/arch/m68k/platform/coldfire/Makefile +++ b/arch/m68k/platform/coldfire/Makefile @@ -20,7 +20,7 @@ obj-$(CONFIG_M5206e) += m5206.o timers.o intc.o reset.o obj-$(CONFIG_M520x) += m520x.o pit.o intc-simr.o reset.o obj-$(CONFIG_M523x) += m523x.o pit.o dma_timer.o intc-2.o reset.o obj-$(CONFIG_M5249) += m5249.o timers.o intc.o intc-5249.o reset.o -obj-$(CONFIG_M527x) += pit.o intc-2.o reset.o +obj-$(CONFIG_M527x) += m527x.o pit.o intc-2.o reset.o obj-$(CONFIG_M5272) += m5272.o intc-5272.o timers.o obj-$(CONFIG_M528x) += pit.o intc-2.o reset.o obj-$(CONFIG_M5307) += timers.o intc.o reset.o diff --git a/arch/m68k/platform/coldfire/m527x.c b/arch/m68k/platform/coldfire/m527x.c new file mode 100644 index 000000000000..9b0b66aabd1b --- /dev/null +++ b/arch/m68k/platform/coldfire/m527x.c @@ -0,0 +1,141 @@ +/***************************************************************************/ + +/* + * linux/arch/m68knommu/platform/527x/config.c + * + * Sub-architcture dependent initialization code for the Freescale + * 5270/5271 CPUs. + * + * Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com) + * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com) + */ + +/***************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/***************************************************************************/ + +struct mcf_gpio_chip mcf_gpio_chips[] = { +#if defined(CONFIG_M5271) + MCFGPS(PIRQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR), + MCFGPF(ADDR, 13, 3), + MCFGPF(DATAH, 16, 8), + MCFGPF(DATAL, 24, 8), + MCFGPF(BUSCTL, 32, 8), + MCFGPF(BS, 40, 4), + MCFGPF(CS, 49, 7), + MCFGPF(SDRAM, 56, 6), + MCFGPF(FECI2C, 64, 4), + MCFGPF(UARTH, 72, 2), + MCFGPF(UARTL, 80, 8), + MCFGPF(QSPI, 88, 5), + MCFGPF(TIMER, 96, 8), +#elif defined(CONFIG_M5275) + MCFGPS(PIRQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR), + MCFGPF(BUSCTL, 8, 8), + MCFGPF(ADDR, 21, 3), + MCFGPF(CS, 25, 7), + MCFGPF(FEC0H, 32, 8), + MCFGPF(FEC0L, 40, 8), + MCFGPF(FECI2C, 48, 6), + MCFGPF(QSPI, 56, 7), + MCFGPF(SDRAM, 64, 8), + MCFGPF(TIMERH, 72, 4), + MCFGPF(TIMERL, 80, 4), + MCFGPF(UARTL, 88, 8), + MCFGPF(FEC1H, 96, 8), + MCFGPF(FEC1L, 104, 8), + MCFGPF(BS, 114, 2), + MCFGPF(IRQ, 121, 7), + MCFGPF(USBH, 128, 1), + MCFGPF(USBL, 136, 8), + MCFGPF(UARTH, 144, 4), +#endif +}; + +unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); + +/***************************************************************************/ + +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) + +static void __init m527x_qspi_init(void) +{ +#if defined(CONFIG_M5271) + u16 par; + + /* setup QSPS pins for QSPI with gpio CS control */ + writeb(0x1f, MCFGPIO_PAR_QSPI); + /* and CS2 & CS3 as gpio */ + par = readw(MCFGPIO_PAR_TIMER); + par &= 0x3f3f; + writew(par, MCFGPIO_PAR_TIMER); +#elif defined(CONFIG_M5275) + /* setup QSPS pins for QSPI with gpio CS control */ + writew(0x003e, MCFGPIO_PAR_QSPI); +#endif +} + +#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ + +/***************************************************************************/ + +static void __init m527x_uarts_init(void) +{ + u16 sepmask; + + /* + * External Pin Mask Setting & Enable External Pin for Interface + */ + sepmask = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART); + sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK; + writew(sepmask, MCF_IPSBAR + MCF_GPIO_PAR_UART); +} + +/***************************************************************************/ + +static void __init m527x_fec_init(void) +{ + u16 par; + u8 v; + + /* Set multi-function pins to ethernet mode for fec0 */ +#if defined(CONFIG_M5271) + v = readb(MCF_IPSBAR + 0x100047); + writeb(v | 0xf0, MCF_IPSBAR + 0x100047); +#else + par = readw(MCF_IPSBAR + 0x100082); + writew(par | 0xf00, MCF_IPSBAR + 0x100082); + v = readb(MCF_IPSBAR + 0x100078); + writeb(v | 0xc0, MCF_IPSBAR + 0x100078); + + /* Set multi-function pins to ethernet mode for fec1 */ + par = readw(MCF_IPSBAR + 0x100082); + writew(par | 0xa0, MCF_IPSBAR + 0x100082); + v = readb(MCF_IPSBAR + 0x100079); + writeb(v | 0xc0, MCF_IPSBAR + 0x100079); +#endif +} + +/***************************************************************************/ + +void __init config_BSP(char *commandp, int size) +{ + mach_sched_init = hw_timer_init; + m527x_uarts_init(); + m527x_fec_init(); +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) + m527x_qspi_init(); +#endif +} + +/***************************************************************************/ -- cgit v1.2.3-59-g8ed1b