From 98d8a60eccee74165793379f1f8a3b1cef3131c7 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Mon, 29 Jun 2015 16:56:30 -0700 Subject: clk: Convert __clk_get_flags() to clk_hw_get_flags() Mostly converted with the following snippet: @@ struct clk_hw *E; @@ -__clk_get_flags(E->clk) +clk_hw_get_flags(E) Acked-by: Tero Kristo Cc: Maxime Ripard Cc: Max Filippov Acked-by: Sebastian Hesselbarth Cc: Daniel Thompson Cc: Coquelin Signed-off-by: Stephen Boyd --- drivers/clk/clk-si5351.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/clk/clk-si5351.c') diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c index 9e6de57eae3b..4b2ee39f05fd 100644 --- a/drivers/clk/clk-si5351.c +++ b/drivers/clk/clk-si5351.c @@ -663,7 +663,7 @@ static long si5351_msynth_round_rate(struct clk_hw *hw, unsigned long rate, divby4 = 1; /* multisync can set pll */ - if (__clk_get_flags(hwdata->hw.clk) & CLK_SET_RATE_PARENT) { + if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { /* * find largest integer divider for max * vco frequency and given target rate @@ -1013,7 +1013,7 @@ static long si5351_clkout_round_rate(struct clk_hw *hw, unsigned long rate, rate = SI5351_CLKOUT_MIN_FREQ; /* request frequency if multisync master */ - if (__clk_get_flags(hwdata->hw.clk) & CLK_SET_RATE_PARENT) { + if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { /* use r divider for frequencies below 1MHz */ rdiv = SI5351_OUTPUT_CLK_DIV_1; while (rate < SI5351_MULTISYNTH_MIN_FREQ && -- cgit v1.2.3-59-g8ed1b