From 98ee8b2f66ebff2fafe85668b9d00c3433b76566 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 3 Dec 2021 11:51:49 +0000 Subject: clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro Rename the macro CLK_PLL3_DIV4->CLK_PLL3_DIV2_2 to match the clock tree mentioned in the hardware manual(Rev.1.00 Sep, 2021). Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20211203115154.31864-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g044-cpg.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/clk/renesas') diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index a91ccad6329b..0962f25cd3f0 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -32,9 +32,9 @@ enum clk_ids { CLK_PLL3_400, CLK_PLL3_533, CLK_PLL3_DIV2, + CLK_PLL3_DIV2_2, CLK_PLL3_DIV2_4, CLK_PLL3_DIV2_4_2, - CLK_PLL3_DIV4, CLK_SEL_PLL3_3, CLK_DIV_PLL3_C, CLK_PLL4, @@ -106,9 +106,9 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10), DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), + DEF_FIXED(".pll3_div2_2", CLK_PLL3_DIV2_2, CLK_PLL3_DIV2, 1, 2), DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2), - DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4), DEF_MUX(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3, ARRAY_SIZE(sel_pll3_3), 0, CLK_MUX_READ_ONLY), DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, -- cgit v1.2.3-59-g8ed1b