From 13e0dde8b2ed043aa3e65437342d501715d975c1 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 19 May 2017 15:06:08 +0800 Subject: clk: sunxi-ng: Support multiple variable pre-dividers On the A83T, the AHB1 clock has a shared pre-divider on the two PLL-PERIPH clock parents. To support such instances of shared pre-dividers, this patch extends the mux clock type to support multiple variable pre-dividers. As the pre-dividers are only used to calculate the rate, but do not participate in the factorization process, this is fairly straightforward. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers/clk/sunxi-ng/ccu-sun8i-v3s.c') diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c index 6297add857b5..a34a78d7fb28 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c @@ -132,6 +132,9 @@ static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x050, 0, 2, 0); static const char * const ahb1_parents[] = { "osc32k", "osc24M", "axi", "pll-periph0" }; +static const struct ccu_mux_var_prediv ahb1_predivs[] = { + { .index = 3, .shift = 6, .width = 2 }, +}; static struct ccu_div ahb1_clk = { .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), @@ -139,11 +142,8 @@ static struct ccu_div ahb1_clk = { .shift = 12, .width = 2, - .variable_prediv = { - .index = 3, - .shift = 6, - .width = 2, - }, + .var_predivs = ahb1_predivs, + .n_var_predivs = ARRAY_SIZE(ahb1_predivs), }, .common = { -- cgit v1.2.3-59-g8ed1b