From 407254da291c03c32109881ca8cbda5607714a8f Mon Sep 17 00:00:00 2001 From: Rhyland Klein Date: Thu, 18 Jun 2015 17:28:25 -0400 Subject: clk: tegra: pll: Add logic for out-of-table rates for T210 For Tegra210, the logic to calculate out-of-table rates is different from previous generations. Add callbacks that can be overridden to allow for different ways of calculating rates. Default to _cal_rate when not specified. This patch also includes a new flag which is used to set which method of fixed_mdiv calculation is used. The new method for calculating the fixed divider value for M can be more accurate especially when fractional dividers are in play. This allows for older chipsets to use the existing logic and new generations to use a newer version which may work better for them. Based on original work by Aleksandr Frid Reviewed-by: Benson Leung Signed-off-by: Rhyland Klein Signed-off-by: Thierry Reding --- drivers/clk/tegra/clk.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'drivers/clk/tegra/clk.h') diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 72368e1ed46a..ae09a3139df2 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -194,8 +194,12 @@ struct div_nmp { * @div_nmp: offsets and widths on n, m and p fields * @freq_table: array of frequencies supported by PLL * @fixed_rate: PLL rate if it is fixed + * @mdiv_default: Default value for fixed mdiv for this PLL + * @round_p_to_pdiv: Callback used to round p to the closed pdiv * @set_gain: Callback to adjust N div for SDM enabled * PLL's based on fractional divider value. + * @calc_rate: Callback used to change how out of table + * rates (dividers and multipler) are calculated. * * Flags: * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for @@ -217,6 +221,8 @@ struct div_nmp { * base register. * TEGRA_PLL_BYPASS - PLL has bypass bit * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring + * TEGRA_MDIV_NEW - Switch to new method for calculating fixed mdiv + * it may be more accurate (especially if SDM present) */ struct tegra_clk_pll_params { unsigned long input_min; @@ -251,7 +257,12 @@ struct tegra_clk_pll_params { struct div_nmp *div_nmp; struct tegra_clk_pll_freq_table *freq_table; unsigned long fixed_rate; + u16 mdiv_default; + u32 (*round_p_to_pdiv)(u32 p, u32 *pdiv); void (*set_gain)(struct tegra_clk_pll_freq_table *cfg); + int (*calc_rate)(struct clk_hw *hw, + struct tegra_clk_pll_freq_table *cfg, + unsigned long rate, unsigned long parent_rate); }; #define TEGRA_PLL_USE_LOCK BIT(0) @@ -265,6 +276,7 @@ struct tegra_clk_pll_params { #define TEGRA_PLL_LOCK_MISC BIT(8) #define TEGRA_PLL_BYPASS BIT(9) #define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10) +#define TEGRA_MDIV_NEW BIT(11) /** * struct tegra_clk_pll - Tegra PLL clock @@ -690,5 +702,6 @@ void tegra114_clock_deassert_dfll_dvco_reset(void); typedef void (*tegra_clk_apply_init_table_func)(void); extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table; int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll); +u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate); #endif /* TEGRA_CLK_H */ -- cgit v1.2.3-59-g8ed1b