From b64ce7cd7f540c64e3fbeaeee3ddb59bc9ab1a3b Mon Sep 17 00:00:00 2001 From: Yazen Ghannam Date: Thu, 17 Nov 2016 17:57:37 -0500 Subject: EDAC, amd64: Read MC registers on AMD Fam17h Fam17h has a different set of registers and bitfields. Most of these registers are read through SMN (System Management Network) rather than PCI config space. Also, the derivation of various values is now different. Update amd64_edac to read the appropriate registers and extract the correct values for Fam17h. Signed-off-by: Yazen Ghannam Cc: Aravind Gopalakrishnan Cc: linux-edac Cc: x86-ml Link: http://lkml.kernel.org/r/1479423463-8536-12-git-send-email-Yazen.Ghannam@amd.com [ Save us the indentation level in read_mc_regs(), add defines ] Signed-off-by: Borislav Petkov --- drivers/edac/amd64_edac.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'drivers/edac/amd64_edac.h') diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 4ca7d249f02e..738166393673 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -250,12 +250,23 @@ /* MSRs */ #define MSR_MCGCTL_NBE BIT(4) +/* F17h */ + +/* F0: */ +#define DF_DHAR 0x104 + /* UMC CH register offsets */ +#define UMCCH_BASE_ADDR 0x0 +#define UMCCH_ADDR_MASK 0x20 +#define UMCCH_DIMM_CFG 0x80 #define UMCCH_SDP_CTRL 0x104 +#define UMCCH_ECC_CTRL 0x14C #define UMCCH_UMC_CAP_HI 0xDF4 /* UMC CH bitfields */ +#define UMC_ECC_CHIPKILL_CAP BIT(31) #define UMC_ECC_ENABLED BIT(30) + #define UMC_SDP_INIT BIT(31) #define NUM_UMCS 2 @@ -302,7 +313,9 @@ struct chip_select { }; struct amd64_umc { + u32 dimm_cfg; /* DIMM Configuration reg */ u32 sdp_ctrl; /* SDP Control reg */ + u32 ecc_ctrl; /* DRAM ECC Control reg */ }; struct amd64_pvt { -- cgit v1.2.3-59-g8ed1b