From f7df8c92b4b90a891972fb782b3eaac836efa601 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Mon, 13 May 2019 14:30:04 -0700 Subject: clk: sifive: restrict Kconfig scope for the FU540 PRCI driver Restrict Kconfig scope for SiFive clock and reset IP block drivers such that they won't appear on most configurations that are unlikely to support them. This is based on a suggestion from Pavel Machek . Ideally this should be dependent on CONFIG_ARCH_SIFIVE, but since that Kconfig directive does not yet exist, add dependencies on RISCV or COMPILE_TEST for now. Signed-off-by: Paul Walmsley Signed-off-by: Paul Walmsley Reported-by: Pavel Machek Cc: Michael Turquette Acked-by: Pavel Machek Signed-off-by: Stephen Boyd --- drivers/clk/sifive/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig index 8db4a3eb4782..f3b4eb9cb0f5 100644 --- a/drivers/clk/sifive/Kconfig +++ b/drivers/clk/sifive/Kconfig @@ -2,6 +2,7 @@ menuconfig CLK_SIFIVE bool "SiFive SoC driver support" + depends on RISCV || COMPILE_TEST help SoC drivers for SiFive Linux-capable SoCs. -- cgit v1.2.3-59-g8ed1b From b3fddd5b100e4aee4f7ec58360435024971dea47 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 20 May 2019 02:03:19 +0000 Subject: clk: imx: imx8mm: fix int pll clk gate To Frac pll, the gate shift is 13, however to Int PLL the gate shift is 11. Cc: Fixes: ba5625c3e27 ("clk: imx: Add clock driver support for imx8mm") Signed-off-by: Peng Fan Reviewed-by: Fabio Estevam Reviewed-by: Jacky Bai Signed-off-by: Stephen Boyd --- drivers/clk/imx/clk-imx8mm.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 1ef8438e3d6d..122a81ab8e48 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -449,12 +449,12 @@ static int __init imx8mm_clocks_init(struct device_node *ccm_node) clks[IMX8MM_AUDIO_PLL2_OUT] = imx_clk_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13); clks[IMX8MM_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out", "video_pll1_bypass", base + 0x28, 13); clks[IMX8MM_DRAM_PLL_OUT] = imx_clk_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13); - clks[IMX8MM_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 13); - clks[IMX8MM_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 13); - clks[IMX8MM_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 13); - clks[IMX8MM_SYS_PLL1_OUT] = imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 13); - clks[IMX8MM_SYS_PLL2_OUT] = imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 13); - clks[IMX8MM_SYS_PLL3_OUT] = imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 13); + clks[IMX8MM_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11); + clks[IMX8MM_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 11); + clks[IMX8MM_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11); + clks[IMX8MM_SYS_PLL1_OUT] = imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11); + clks[IMX8MM_SYS_PLL2_OUT] = imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11); + clks[IMX8MM_SYS_PLL3_OUT] = imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11); /* SYS PLL fixed output */ clks[IMX8MM_SYS_PLL1_40M] = imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20); -- cgit v1.2.3-59-g8ed1b From 1cc54078d104f5b4d7e9f8d55362efa5a8daffdb Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 6 May 2019 14:08:54 -0700 Subject: clk: ti: clkctrl: Fix clkdm_clk handling We need to always call clkdm_clk_enable() and clkdm_clk_disable() even the clkctrl clock(s) enabled for the domain do not have any gate register bits. Otherwise clockdomains may never get enabled except when devices get probed with the legacy "ti,hwmods" devicetree property. Fixes: 88a172526c32 ("clk: ti: add support for clkctrl clocks") Signed-off-by: Tony Lindgren Signed-off-by: Stephen Boyd --- drivers/clk/ti/clkctrl.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c index 96d65a1cf7be..8e834317c97d 100644 --- a/drivers/clk/ti/clkctrl.c +++ b/drivers/clk/ti/clkctrl.c @@ -137,9 +137,6 @@ static int _omap4_clkctrl_clk_enable(struct clk_hw *hw) int ret; union omap4_timeout timeout = { 0 }; - if (!clk->enable_bit) - return 0; - if (clk->clkdm) { ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk); if (ret) { @@ -151,6 +148,9 @@ static int _omap4_clkctrl_clk_enable(struct clk_hw *hw) } } + if (!clk->enable_bit) + return 0; + val = ti_clk_ll_ops->clk_readl(&clk->enable_reg); val &= ~OMAP4_MODULEMODE_MASK; @@ -179,7 +179,7 @@ static void _omap4_clkctrl_clk_disable(struct clk_hw *hw) union omap4_timeout timeout = { 0 }; if (!clk->enable_bit) - return; + goto exit; val = ti_clk_ll_ops->clk_readl(&clk->enable_reg); -- cgit v1.2.3-59-g8ed1b