From 9d52691f899b843d1e0afa8fca19496ace76b8c7 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 31 Dec 2024 18:32:24 +0530 Subject: PCI: qcom-ep: Mark BAR0/BAR2 as 64bit BARs and BAR1/BAR3 as RESERVED MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On all Qcom endpoint SoCs, BAR0/BAR2 are 64bit BARs by default and software cannot change the type. So, mark the those BARs as 64bit BARs and also mark the successive BAR1/BAR3 as RESERVED BARs so that the EPF drivers cannot use them. Cc: stable+noautosel@kernel.org # depends on patch introducing only_64bit flag Fixes: f55fee56a631 ("PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller driver") Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20241231130224.38206-3-manivannan.sadhasivam@linaro.org [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index c08f64d7a825..01d3862d7003 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -825,6 +825,10 @@ static const struct pci_epc_features qcom_pcie_epc_features = { .msi_capable = true, .msix_capable = false, .align = SZ_4K, + .bar[BAR_0] = { .only_64bit = true, }, + .bar[BAR_1] = { .type = BAR_RESERVED, }, + .bar[BAR_2] = { .only_64bit = true, }, + .bar[BAR_3] = { .type = BAR_RESERVED, }, }; static const struct pci_epc_features * -- cgit v1.2.3-59-g8ed1b From 42c812d07088777a3439e51bd1461d215151150e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 21 Feb 2025 17:52:04 +0200 Subject: PCI: qcom-ep: Enable EP mode support for SAR2130P MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable PCIe Endpoint mode support for the Qualcomm SAR2130P platform. This is needed, as it is not possible to use a compatible fallback on any other platform since SAR2130P uses slightly different set of clocks. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250221-sar2130p-pci-v3-6-61a0fdfb75b4@linaro.org Reviewed-by: Manivannan Sadhasivam Signed-off-by: Krzysztof Wilczyński --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 01d3862d7003..d1f777945680 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -937,6 +937,7 @@ static const struct of_device_id qcom_pcie_ep_match[] = { { .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0}, { .compatible = "qcom,sdx55-pcie-ep", }, { .compatible = "qcom,sm8450-pcie-ep", }, + { .compatible = "qcom,sar2130p-pcie-ep", }, { } }; MODULE_DEVICE_TABLE(of, qcom_pcie_ep_match); -- cgit v1.2.3-59-g8ed1b