From 57b0302240741e73fe51f88404b3866e0d2933ad Mon Sep 17 00:00:00 2001 From: Thippeswamy Havalige Date: Mon, 24 Feb 2025 21:20:22 +0530 Subject: PCI: xilinx-cpm: Fix IRQ domain leak in error path of probe MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The IRQ domain allocated for the PCIe controller is not freed if resource_list_first_type() returns NULL, leading to a resource leak. This fix ensures properly cleaning up the allocated IRQ domain in the error path. Fixes: 49e427e6bdd1 ("Merge branch 'pci/host-probe-refactor'") Signed-off-by: Thippeswamy Havalige [kwilczynski: added missing Fixes: tag, refactored to use one of the goto labels] Signed-off-by: Krzysztof Wilczyński Link: https://lore.kernel.org/r/20250224155025.782179-2-thippeswamy.havalige@amd.com --- drivers/pci/controller/pcie-xilinx-cpm.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/controller/pcie-xilinx-cpm.c index 81e8bfae53d0..dc8ecdbee56c 100644 --- a/drivers/pci/controller/pcie-xilinx-cpm.c +++ b/drivers/pci/controller/pcie-xilinx-cpm.c @@ -583,15 +583,17 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev) return err; bus = resource_list_first_type(&bridge->windows, IORESOURCE_BUS); - if (!bus) - return -ENODEV; + if (!bus) { + err = -ENODEV; + goto err_free_irq_domains; + } port->variant = of_device_get_match_data(dev); err = xilinx_cpm_pcie_parse_dt(port, bus->res); if (err) { dev_err(dev, "Parsing DT failed\n"); - goto err_parse_dt; + goto err_free_irq_domains; } xilinx_cpm_pcie_init_port(port); @@ -615,7 +617,7 @@ err_host_bridge: xilinx_cpm_free_interrupts(port); err_setup_irq: pci_ecam_free(port->cfg); -err_parse_dt: +err_free_irq_domains: xilinx_cpm_free_irq_domains(port); return err; } -- cgit v1.2.3-59-g8ed1b From ad3b7174d4d04b7e2ab81df5857c4da6b4bc1ade Mon Sep 17 00:00:00 2001 From: Thippeswamy Havalige Date: Mon, 24 Feb 2025 21:20:24 +0530 Subject: PCI: xilinx-cpm: Add support for Versal Net CPM5NC Root Port controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Versal Net ACAP (Adaptive Compute Acceleration Platform) devices incorporate the Coherency and PCIe Gen5 Module, specifically the Next-Generation Compact Module (CPM5NC). The integrated CPM5NC block, along with the built-in bridge, can function as a PCIe Root Port and supports the PCIe Gen5 protocol with data transfer rates of up to 32 GT/s, and is capable of supporting up to a x16 lane-width configuration. Bridge errors are managed using a specific interrupt line designed for CPM5N. The INTx interrupt support is not available. Currently in this commit platform specific bridge errors support is not added. Signed-off-by: Thippeswamy Havalige [kwilczynski: commit log, squashed patch to fix an if-statement condition to ensure that xilinx_cpm_pcie_init_port() does not run on the CPM5NC_HOST variant from https://lore.kernel.org/linux-pci/20250311072402.1049990-1-thippeswamy.havalige@amd.com] Signed-off-by: Krzysztof Wilczyński Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20250224155025.782179-4-thippeswamy.havalige@amd.com --- drivers/pci/controller/pcie-xilinx-cpm.c | 40 +++++++++++++++++++++++--------- 1 file changed, 29 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/controller/pcie-xilinx-cpm.c index dc8ecdbee56c..d0ab187d917f 100644 --- a/drivers/pci/controller/pcie-xilinx-cpm.c +++ b/drivers/pci/controller/pcie-xilinx-cpm.c @@ -84,6 +84,7 @@ enum xilinx_cpm_version { CPM, CPM5, CPM5_HOST1, + CPM5NC_HOST, }; /** @@ -478,6 +479,9 @@ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port) { const struct xilinx_cpm_variant *variant = port->variant; + if (variant->version == CPM5NC_HOST) + return; + if (cpm_pcie_link_up(port)) dev_info(port->dev, "PCIe Link is UP\n"); else @@ -578,9 +582,13 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev) port->dev = dev; - err = xilinx_cpm_pcie_init_irq_domain(port); - if (err) - return err; + port->variant = of_device_get_match_data(dev); + + if (port->variant->version != CPM5NC_HOST) { + err = xilinx_cpm_pcie_init_irq_domain(port); + if (err) + return err; + } bus = resource_list_first_type(&bridge->windows, IORESOURCE_BUS); if (!bus) { @@ -588,8 +596,6 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev) goto err_free_irq_domains; } - port->variant = of_device_get_match_data(dev); - err = xilinx_cpm_pcie_parse_dt(port, bus->res); if (err) { dev_err(dev, "Parsing DT failed\n"); @@ -598,10 +604,12 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev) xilinx_cpm_pcie_init_port(port); - err = xilinx_cpm_setup_irq(port); - if (err) { - dev_err(dev, "Failed to set up interrupts\n"); - goto err_setup_irq; + if (port->variant->version != CPM5NC_HOST) { + err = xilinx_cpm_setup_irq(port); + if (err) { + dev_err(dev, "Failed to set up interrupts\n"); + goto err_setup_irq; + } } bridge->sysdata = port->cfg; @@ -614,11 +622,13 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev) return 0; err_host_bridge: - xilinx_cpm_free_interrupts(port); + if (port->variant->version != CPM5NC_HOST) + xilinx_cpm_free_interrupts(port); err_setup_irq: pci_ecam_free(port->cfg); err_free_irq_domains: - xilinx_cpm_free_irq_domains(port); + if (port->variant->version != CPM5NC_HOST) + xilinx_cpm_free_irq_domains(port); return err; } @@ -641,6 +651,10 @@ static const struct xilinx_cpm_variant cpm5_host1 = { .ir_enable = XILINX_CPM_PCIE1_IR_ENABLE, }; +static const struct xilinx_cpm_variant cpm5n_host = { + .version = CPM5NC_HOST, +}; + static const struct of_device_id xilinx_cpm_pcie_of_match[] = { { .compatible = "xlnx,versal-cpm-host-1.00", @@ -654,6 +668,10 @@ static const struct of_device_id xilinx_cpm_pcie_of_match[] = { .compatible = "xlnx,versal-cpm5-host1", .data = &cpm5_host1, }, + { + .compatible = "xlnx,versal-cpm5nc-host", + .data = &cpm5n_host, + }, {} }; -- cgit v1.2.3-59-g8ed1b From 9e141923cf86b2e1c83d21b87fb4de3d14a20c99 Mon Sep 17 00:00:00 2001 From: Thippeswamy Havalige Date: Mon, 17 Mar 2025 18:11:36 +0530 Subject: PCI: xilinx-cpm: Add cpm_csr register mapping for CPM5_HOST1 variant MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the CPM5 check to include CPM5_HOST1 variant. Previously, only CPM5 was considered when mapping the "cpm_csr" register. With this change, CPM5_HOST1 is also supported, ensuring proper resource mapping for this variant. Signed-off-by: Thippeswamy Havalige [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński Link: https://lore.kernel.org/r/20250317124136.1317723-1-thippeswamy.havalige@amd.com --- drivers/pci/controller/pcie-xilinx-cpm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/controller/pcie-xilinx-cpm.c index d0ab187d917f..13ca493d22bd 100644 --- a/drivers/pci/controller/pcie-xilinx-cpm.c +++ b/drivers/pci/controller/pcie-xilinx-cpm.c @@ -542,7 +542,8 @@ static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port, if (IS_ERR(port->cfg)) return PTR_ERR(port->cfg); - if (port->variant->version == CPM5) { + if (port->variant->version == CPM5 || + port->variant->version == CPM5_HOST1) { port->reg_base = devm_platform_ioremap_resource_byname(pdev, "cpm_csr"); if (IS_ERR(port->reg_base)) -- cgit v1.2.3-59-g8ed1b