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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2020 SiFive
*/
#ifndef __ASM_RISCV_VECTOR_H
#define __ASM_RISCV_VECTOR_H
#include <linux/types.h>
#ifdef CONFIG_RISCV_ISA_V
#include <asm/hwcap.h>
#include <asm/csr.h>
static __always_inline bool has_vector(void)
{
return riscv_has_extension_unlikely(RISCV_ISA_EXT_v);
}
static __always_inline void riscv_v_enable(void)
{
csr_set(CSR_SSTATUS, SR_VS);
}
static __always_inline void riscv_v_disable(void)
{
csr_clear(CSR_SSTATUS, SR_VS);
}
#else /* ! CONFIG_RISCV_ISA_V */
static __always_inline bool has_vector(void) { return false; }
#endif /* CONFIG_RISCV_ISA_V */
#endif /* ! __ASM_RISCV_VECTOR_H */
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