blob: 9ede14a125731c4bb0d8a43b5abb9e01326bcf9c (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
|
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Microsemi Ocelot Switch driver
*
* License: Dual MIT/GPL
* Copyright (c) 2017 Microsemi Corporation
*/
#ifndef _MSCC_OCELOT_PTP_H_
#define _MSCC_OCELOT_PTP_H_
#define PTP_PIN_CFG_RSZ 0x20
#define PTP_PIN_TOD_SEC_MSB_RSZ PTP_PIN_CFG_RSZ
#define PTP_PIN_TOD_SEC_LSB_RSZ PTP_PIN_CFG_RSZ
#define PTP_PIN_TOD_NSEC_RSZ PTP_PIN_CFG_RSZ
#define PTP_PIN_CFG_DOM BIT(0)
#define PTP_PIN_CFG_SYNC BIT(2)
#define PTP_PIN_CFG_ACTION(x) ((x) << 3)
#define PTP_PIN_CFG_ACTION_MASK PTP_PIN_CFG_ACTION(0x7)
enum {
PTP_PIN_ACTION_IDLE = 0,
PTP_PIN_ACTION_LOAD,
PTP_PIN_ACTION_SAVE,
PTP_PIN_ACTION_CLOCK,
PTP_PIN_ACTION_DELTA,
PTP_PIN_ACTION_NOSYNC,
PTP_PIN_ACTION_SYNC,
};
#define PTP_CFG_MISC_PTP_EN BIT(2)
#define PSEC_PER_SEC 1000000000000LL
#define PTP_CFG_CLK_ADJ_CFG_ENA BIT(0)
#define PTP_CFG_CLK_ADJ_CFG_DIR BIT(1)
#define PTP_CFG_CLK_ADJ_FREQ_NS BIT(30)
#endif
|
