blob: 4b04dabacec2ccaa89bc2d4875d60d8f3d18f2b2 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
|
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2019 Microchip Inc.
*
* Author: Lars Povlsen <lars.povlsen@microchip.com>
*/
#ifndef _DT_BINDINGS_CLK_SPARX5_H
#define _DT_BINDINGS_CLK_SPARX5_H
#define CLK_ID_CORE 0
#define CLK_ID_DDR 1
#define CLK_ID_CPU2 2
#define CLK_ID_ARM2 3
#define CLK_ID_AUX1 4
#define CLK_ID_AUX2 5
#define CLK_ID_AUX3 6
#define CLK_ID_AUX4 7
#define CLK_ID_SYNCE 8
#define N_CLOCKS 9
#endif
|
