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| author |   René van Dorst <opensource@vdorst.com> | 2018-05-19 20:55:42 +0200 |
|---|---|---|
| committer |   Jason A. Donenfeld <Jason@zx2c4.com> | 2018-05-30 03:22:20 +0200 |
| commit | 6f8f15b98b30eb8f40fbedf282b4b64aa1a0d134 (patch) | |
| tree | 5e751f52a95a87947918deaf916e0f64704f4c12 | |
| parent | wg-quick: darwin: set DNS servers after delay on route change (diff) | |
| download | wireguard-monolithic-historical-6f8f15b98b30eb8f40fbedf282b4b64aa1a0d134.tar.xz wireguard-monolithic-historical-6f8f15b98b30eb8f40fbedf282b4b64aa1a0d134.zip | |
poly1305: mips: remove unused S0 allocation
Signed-off-by: René van Dorst <opensource@vdorst.com>
| -rw-r--r-- | src/crypto/poly1305-mips.S | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/src/crypto/poly1305-mips.S b/src/crypto/poly1305-mips.S index cd62d9b..095718c 100644 --- a/src/crypto/poly1305-mips.S +++ b/src/crypto/poly1305-mips.S @@ -44,10 +44,14 @@ #define srclen $a2 #define hibit $a3 +/* Location on the Opaque buffer. + * R[0..3], S[1..3], CA, H[0..4]. + * Because S0 is not used we add a -4 offset. + */ #define PTR_POLY1305_R(n) ( 0 + (n*4)) ## ($a0) -#define PTR_POLY1305_S(n) (16 + (n*4)) ## ($a0) -#define PTR_POLY1305_CA (32 ) ## ($a0) -#define PTR_POLY1305_H(n) (36 + (n*4)) ## ($a0) +#define PTR_POLY1305_S(n) (16 - 4 + (n*4)) ## ($a0) +#define PTR_POLY1305_CA (28 ) ## ($a0) +#define PTR_POLY1305_H(n) (32 + (n*4)) ## ($a0) #define POLY1305_BLOCK_SIZE 16 #define POLY1305_STACK_SIZE 8 * 4 @@ -58,7 +62,7 @@ .globl poly1305_blocks_mips .ent poly1305_blocks_mips poly1305_blocks_mips: - .frame $sp,POLY1305_STACK_SIZE,$31 + .frame $sp, POLY1305_STACK_SIZE, $ra /* srclen &= 0xFFFFFFF0 */ ins srclen, $zero, 0, 4 @@ -73,6 +77,7 @@ poly1305_blocks_mips: */ addu srclen, src + /* load Rx */ lw R0, PTR_POLY1305_R(0) lw R1, PTR_POLY1305_R(1) lw R2, PTR_POLY1305_R(2) @@ -86,11 +91,10 @@ poly1305_blocks_mips: sw $s4, 16($sp) sw $s5, 20($sp) + /* load Sx, Hx and Carry */ lw S1, PTR_POLY1305_S(1) lw S2, PTR_POLY1305_S(2) lw S3, PTR_POLY1305_S(3) - - /* load Hx and Carry */ lw CA, PTR_POLY1305_CA lw H0, PTR_POLY1305_H(0) lw H1, PTR_POLY1305_H(1) @@ -101,6 +105,7 @@ poly1305_blocks_mips: addiu SC, $zero, 1 .Lpoly1305_loop: + /* load src */ lwl O0, 0+MSB(src) lwl O1, 4+MSB(src) lwl O2, 8+MSB(src) |