WireGuard implementation for the OpenBSD kernel https://git.zx2c4.com/wireguard-openbsd/atom/gnu/llvm/lib?h=jd%2Fsimplify-queueing 2020-06-04T22:33:17Z 2020-06-04T22:33:17Z gkoehler gkoehler@openbsd.org 2020-06-04T22:33:17Z urn:sha1:21ddc59af3b7bf4d9a666653828d7e9ee41cba12 32-bit PowerPC doesn't have instructions for lock-free atomic ops on 8-byte values, and needs libcalls like __atomic_fetch_add_8(). In code like "_Atomic long long a; a++;", clang doesn't emit a libcall. This was causing linker errors on symbols like __sync_fetch_and_add_8. Now that LLVM knows the max atomic size, its AtomicExpandPass changes these 8-byte ops into libcalls. ok mortimer@ 2020-05-30T19:27:11Z drahn drahn@openbsd.org 2020-05-30T19:27:11Z urn:sha1:98c52506dedbd7b4b3f76d15c419a7ea974c7fb5 This should simplify bringup and make it easier to support Big Endian and Little Endian with the same code. May be reconsidered if it causes too many problems with Ports. ok kettenis@ 2020-05-23T07:18:50Z visa visa@openbsd.org 2020-05-23T07:18:50Z urn:sha1:59447aca8d09daa7e01d4745dffe3b139396b8c7 This lets the kernel detect retguard traps and send SIGABRT instead of SIGEMT. SIGEMT does not indicate correctly the nature of the error (stack overflow, violation of control flow). It can confuse the user to restart the program without further investigation. Prompted by and OK deraadt@ OK mortimer@ 2020-05-02T05:34:08Z gkoehler gkoehler@openbsd.org 2020-05-02T05:34:08Z urn:sha1:ffca677e9e7ca9efd316fa2f2b6572b193c50cf8 When the DAG truncates an ISD::ADDE node, DAGCombiner may optimize it by making an adde with smaller operands. PowerPC has i1 registers, and may truncate an i32 adde to i1, but an i1 adde is not legal for PowerPC, and the legalize-ops phase can't fix it. This was causing "fatal error: error in backend: Cannot select..." cwen@ reported the error ok mortimer@ kettenis@ deraadt@ 2020-04-09T17:08:56Z kettenis kettenis@openbsd.org 2020-04-09T17:08:56Z urn:sha1:00f51392e3b69b727541e329a65fd30b7f432c5e "hard-quad-float" feature is available. Add missing replacement instruction patterns that are needed to emit alternative code for conditional moves of quad-precision floats. ok mortimer@ 2020-04-04T09:54:04Z kettenis kettenis@openbsd.org 2020-04-04T09:54:04Z urn:sha1:3159fc8f233e5ccb749cd05b58cf5b93b8f45263 ok mortimer@ 2019-11-09T20:29:08Z guenther guenther@openbsd.org 2019-11-09T20:29:08Z urn:sha1:0a276a5089a34f31ea48f000c0ffe0023990ca5d them as COMDATs so that the linker can individually discard them, instead of just ignoring duplicate symbols but keep the (duplicate) space. On amd64, this reduces the size of the kernel OPENBSD_RANDOM segment by 82% and the libc OPENBSD_RANDOM segment by 15%. A port that tb@ is working on experienced a 97.3% reduction...which let it actually run. ok mortimer@ deraadt@ 2019-10-25T00:40:56Z mortimer mortimer@openbsd.org 2019-10-25T00:40:56Z urn:sha1:52446778f86252aa4533d0b08b871472df4e84f6 For this architecture we use separate retguard prologue and epilogue code for static or PIC code. In the PIC case we use some additional code before the retguard epilogue to recover the function start address and the GOT pointer in order to get the per-function random cookie. Much thanks to visa@ for suggestions and advice making it all work. ok deraadt@ visa@ 2019-09-01T16:37:21Z patrick patrick@openbsd.org 2019-09-01T16:37:21Z urn:sha1:d3df0c01b52bb561f932539d0321079fcb70e869 Tested in snaps and package builds Tested on amd64 by naddy@ Tested on arm64 by patrick@ Tested on octeon by visa@ 2019-09-01T16:27:59Z patrick patrick@openbsd.org 2019-09-01T16:27:59Z urn:sha1:b19884b112052f3bf5ff9551374fbd840e2339f2