wireguard-openbsd/lib/libm/arch, branch master WireGuard implementation for the OpenBSD kernel https://git.zx2c4.com/wireguard-openbsd/atom/lib/libm/arch?h=master 2020-11-07T11:56:40Z Fix ilogb(3) implementation. The results have to match FP_ILOGB0 and 2020-11-07T11:56:40Z kettenis kettenis@openbsd.org 2020-11-07T11:56:40Z urn:sha1:250365d1ba7d1d2d08b83147fec77890b45476a2 FP_ILOGBNAN which isn't the case for the amd64 and i386 assembly versions. Drop these in favour of C implementations. Als reimplement ilogbl(3) by providing separate ld80 and ld128 implementations that replace the existing implementation which may hit an infinite loop when built for quad-precision long double. ok patrick@, gkoehler@ The fegetexceptflag() function should not have a DEF_STD. 2020-07-09T22:13:29Z kettenis kettenis@openbsd.org 2020-07-09T22:13:29Z urn:sha1:2a049e6c3f852e5c6ff123a1a1b89bce437d94d9 Brings arm64 in line with all the other architectures. ok millert@ Add powerpc64 fenv bits; copied from powerpc. From drahn@ 2020-06-28T08:19:34Z kettenis kettenis@openbsd.org 2020-06-28T08:19:34Z urn:sha1:c931458ee0ebe3f5cf0c8e2202a9b6caa59d413c Setting and getting the rounding mode on our arm64 FPU has not worked 2019-03-12T22:14:50Z patrick patrick@openbsd.org 2019-03-12T22:14:50Z urn:sha1:53b00876ee12a0c62c3f155b1de308a45679f18e in libm since the rounding mode is in fpcr, not fpsr. Since both FPU registers are 32-bit we can store them in the 64-bit fenv_t to make handling the bits easier. While there add FE_DENORMAL, which also exists on x86. Also make sure that whenever we are being passed an exception mask, we only allow the bits that are supported by hardware. Found by regression tests Debugged with Moritz Buhl ok kettenis@ Add missing retguard check 2018-07-08T12:49:16Z mortimer mortimer@openbsd.org 2018-07-08T12:49:16Z urn:sha1:f02487654d2a17e384c1733cbed4444bb30bba52 ok deraadt Add retguard macros to libm assembly. 2018-07-03T22:43:34Z mortimer mortimer@openbsd.org 2018-07-03T22:43:34Z urn:sha1:3ba7702be0c7af3f580acc0a15f2fb78868ef980 ok deraadt Since most (if not all) ARMv8 hardware doesn't actually support trapping of 2018-03-16T10:22:52Z kettenis kettenis@openbsd.org 2018-03-16T10:22:52Z urn:sha1:1ff8d394f3ae9f209c103a45737dbc8f39da325b floating-point exceptions, simplify the functions that control the exception masks just like we did on armv7. ok tom@ Make the binding of rintl, significand, and significandf consistently 2018-03-12T04:27:48Z guenther guenther@openbsd.org 2018-03-12T04:27:48Z urn:sha1:d17b7c42c56308448a37b04fda5041f9c413e4fb 'weak' in the static libm.a ok deraadt@ Change floating-point mode/environment control functions to operate on 2018-02-28T11:16:54Z kettenis kettenis@openbsd.org 2018-02-28T11:16:54Z urn:sha1:b02ee2d0b169340f8c05ac869f38b89250c96865 both the hardfloat (FPU registers) and softfloat (software) state. This makes these functions work correctly when mixing hardfloat and softfloat code. Disable trapping for softfloat since most (if not all) ARMv7 and ARMv8 hardware that is on the market doesn't support trapping of floating-point exceptions. ok patrick@ Constants which can go into .rodata 2018-02-05T04:01:49Z deraadt deraadt@openbsd.org 2018-02-05T04:01:49Z urn:sha1:f6b709d44327051d2daaa7bf3b25ca2bc658a081