<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-openbsd/lib/libunwind/src/Registers.hpp, branch jd/simplify-queueing</title>
<subtitle>WireGuard implementation for the OpenBSD kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-openbsd/atom/lib/libunwind/src/Registers.hpp?h=jd%2Fsimplify-queueing</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-openbsd/atom/lib/libunwind/src/Registers.hpp?h=jd%2Fsimplify-queueing'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-openbsd/'/>
<updated>2020-04-04T14:06:21Z</updated>
<entry>
<title>Fix powerpc libunwind for cpus without altivec.</title>
<updated>2020-04-04T14:06:21Z</updated>
<author>
<name>gkoehler</name>
<email>gkoehler@openbsd.org</email>
</author>
<published>2020-04-04T14:06:21Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-openbsd/commit/?id=233ed438328db8c587872d7af24be341498239b9'/>
<id>urn:sha1:233ed438328db8c587872d7af24be341498239b9</id>
<content type='text'>
Defer saving the altivec registers until we need to access them (like
how arm defers saving the VFP registers).  This prevents a SIGILL on a
G3 cpu when code throws a C++ exception.

ok kettenis@
</content>
</entry>
<entry>
<title>Merge libc++, libc++abi and libunwind version 8.0.0.</title>
<updated>2019-06-17T22:28:47Z</updated>
<author>
<name>patrick</name>
<email>patrick@openbsd.org</email>
</author>
<published>2019-06-17T22:28:47Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-openbsd/commit/?id=308ed93135e1e5919c16767bd98e8835e42e613b'/>
<id>urn:sha1:308ed93135e1e5919c16767bd98e8835e42e613b</id>
<content type='text'>
Ports build by naddy@
Tested by visa on octeon
Tested by kettenis on macppc and sparc64
</content>
</entry>
<entry>
<title>Merge libc++, libc++abi and libunwind version 7.0.1.</title>
<updated>2019-02-04T17:04:33Z</updated>
<author>
<name>patrick</name>
<email>patrick@openbsd.org</email>
</author>
<published>2019-02-04T17:04:33Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-openbsd/commit/?id=71d9f34297ef5b8104aac6236e8dc7c95ff5da15'/>
<id>urn:sha1:71d9f34297ef5b8104aac6236e8dc7c95ff5da15</id>
<content type='text'>
Tested by visa on octeon
Tested by kettenis on arm64, armv7 and sparc64
"go for it" deraadt and sthen
</content>
</entry>
<entry>
<title>Turns out I botched the previous commit.  While making the %o7 + 8 bit</title>
<updated>2019-02-03T15:24:17Z</updated>
<author>
<name>kettenis</name>
<email>kettenis@openbsd.org</email>
</author>
<published>2019-02-03T15:24:17Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-openbsd/commit/?id=904ff9a2689ab293783b1642bea8f3b81bc01042'/>
<id>urn:sha1:904ff9a2689ab293783b1642bea8f3b81bc01042</id>
<content type='text'>
consistent across the various low-level interfaces that handle the
instruction pointer, reality turns out to be a bit more subtle.

On SPARC, DWARF2 uses r15 (which maps to %o7) as the return address column.
This means that we should not add/subtract 8 when it reads/updates the
register state while processing DWARF2 instructions.  That in turn means
that getIP() and setIP() should not have been changed in my previous commit.

ok visa@
</content>
</entry>
<entry>
<title>On SPARC, the return address is %o7 + 8.</title>
<updated>2019-02-03T12:30:02Z</updated>
<author>
<name>kettenis</name>
<email>kettenis@openbsd.org</email>
</author>
<published>2019-02-03T12:30:02Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-openbsd/commit/?id=2f358089abd9682739333c7761ac427883f1e2ae'/>
<id>urn:sha1:2f358089abd9682739333c7761ac427883f1e2ae</id>
<content type='text'>
ok guenther@, deraadt@, patrick@, dlg@, visa@
</content>
</entry>
<entry>
<title>Backport libunwind hardware floating point handling for mips64.</title>
<updated>2018-10-21T05:08:35Z</updated>
<author>
<name>visa</name>
<email>visa@openbsd.org</email>
</author>
<published>2018-10-21T05:08:35Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-openbsd/commit/?id=def71959deb2deb81d76c49c6917229abc5ea77b'/>
<id>urn:sha1:def71959deb2deb81d76c49c6917229abc5ea77b</id>
<content type='text'>
Upstream reference:
https://reviews.llvm.org/D41968

OK kettenis@
</content>
</entry>
<entry>
<title>merge libunwind 6.0.0; ok patrick@, kettenis@</title>
<updated>2018-09-11T18:03:05Z</updated>
<author>
<name>robert</name>
<email>robert@openbsd.org</email>
</author>
<published>2018-09-11T18:03:05Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-openbsd/commit/?id=18617da6761020511f4541a4e88d2854c3e1eb34'/>
<id>urn:sha1:18617da6761020511f4541a4e88d2854c3e1eb34</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Add sparc64 support.</title>
<updated>2017-04-18T15:35:24Z</updated>
<author>
<name>kettenis</name>
<email>kettenis@openbsd.org</email>
</author>
<published>2017-04-18T15:35:24Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-openbsd/commit/?id=60f9c91b81c4e318101a49794c0f84f0961bd10a'/>
<id>urn:sha1:60f9c91b81c4e318101a49794c0f84f0961bd10a</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Import libunwind 3.9.0</title>
<updated>2016-09-03T18:42:12Z</updated>
<author>
<name>patrick</name>
<email>patrick@openbsd.org</email>
</author>
<published>2016-09-03T18:42:12Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-openbsd/commit/?id=03737b27a3148494cc74492e8010677dde089697'/>
<id>urn:sha1:03737b27a3148494cc74492e8010677dde089697</id>
<content type='text'>
</content>
</entry>
</feed>
