wireguard-openbsd/sys/arch/amd64/include, branch masterWireGuard implementation for the OpenBSD kernelhttps://git.zx2c4.com/wireguard-openbsd/atom/sys/arch/amd64/include?h=master2021-03-29T12:39:02ZFix IA32_EPT_VPID_CAP_XO_TRANSLATIONS specification2021-03-29T12:39:02Zdvdv@openbsd.org2021-03-29T12:39:02Zurn:sha1:b134fa217db201f6e402bd40b585b1dd8064d634
Per Intel SDM (Vol 3D, App. A.10) bit 0 should be read as a 1 if enabled.
From Adam Steen. ok mlarkin@
spelling2021-03-11T11:16:54Zjsgjsg@openbsd.org2021-03-11T11:16:54Zurn:sha1:36fd90dcf1acf2ddb4ef5dbabe5313b3a8d46ee2stop showing amd l3 cache information2020-12-22T03:42:03Zjsgjsg@openbsd.org2020-12-22T03:42:03Zurn:sha1:f49709054ac942fc5d0861d4ae958f74aa4bdbe5
>= zen 2 based amd processors return a value of 9 for l3 cache assoc
via cpuid 0x80000006. As that is a reserved value we end up incorrectly
claiming the l3 cache is disabled. While it is possible to get l3 cache
information via cpuid 0x8000001d when TOPEXT is advertised that will
instead give information about the l3 cache available to the core
complex (CCX) that the cpu belongs to where previously the amount of l3
available to all core complexes was shown.
As we don't detail topology in dmesg or show the mapping of cores to
core complexes just stop displaying l3 information. It already isn't
shown on intel.
ok gkoehler@
Delete unused #defines: T_USER hasn't been used since July 20182020-11-13T23:08:10Zguentherguenther@openbsd.org2020-11-13T23:08:10Zurn:sha1:d5e8f672431dd1f49b14ed3c86c6cd1677af35e4
while TC_TSS and TC_FLAGMASK have _never_ been used
ok kettenis@
Simplify interrupt entry stubs to not push around bogus trapno+err2020-11-12T23:29:16Zguentherguenther@openbsd.org2020-11-12T23:29:16Zurn:sha1:a212cfe0ef084b918c78f833fdf2e0d5e970b715
slots but rather go directly from the iretq frame to an intrframe.
This saves 22 bytes in each of the 148 interrupt entry points.
ok mpi@
Give sizes and types to more functions and objects.2020-11-09T19:29:27Zguentherguenther@openbsd.org2020-11-09T19:29:27Zurn:sha1:02a59bc4e444df06893b562e27ea244c07d5fdbe
No effect on object code, just symbol table accuracy
ok mpi@
Restore abstraction of register saving into macros in frameasm.h2020-11-02T18:32:08Zguentherguenther@openbsd.org2020-11-02T18:32:08Zurn:sha1:bb386764c22da6f60e696c14740cd07b0671e4c2
The Meltdown mitigation work ran right across the previous abstractions;
draw slightly different lines and use separate macros for interrupts
vs traps vs syscall.
The generated ASM for traps and general interrupts is completely
unchanged; the ASM for the four directly routed interrupts is brought
into line with the general interrupts; the ASM for syscalls is
changed to delay reenabling interrupts until after all registers
are saved and cleared.
ok mpi@
Use "memory" on inline fence instructions to suggest to the compiler2020-10-28T09:58:57Zjsgjsg@openbsd.org2020-10-28T09:58:57Zurn:sha1:157282f2b32fff9894012f27bb7ba3d156120d36
it shouldn't optimise across them.
ok kettenis@
Adding IOMMU support for AMD Vi and Intel VTD (disabled)2020-10-27T02:39:07Zjordanjordan@openbsd.org2020-10-27T02:39:07Zurn:sha1:969402718346f9dea55b91cce8485c570c7b090b
This creates separate domains for each PCI device and can provide protection
against invalid memory access. Needed for Passthrough PCI from vmd.
ok deraadt@, kettenis@
: ----------------------------------------------------------------------
Save and restore the MXCSR register and the FPU control word such that2020-10-21T19:00:14Zketteniskettenis@openbsd.org2020-10-21T19:00:14Zurn:sha1:0415c54721ce1b77cc8a3f8978d7d14b2e9085b5
floating-point control modes are properly restored by longjmp(3).
ok guenther@