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<title>wireguard-openbsd/sys/arch/amd64, branch jd/queueboosts</title>
<subtitle>WireGuard implementation for the OpenBSD kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-openbsd/atom/sys/arch/amd64?h=jd%2Fqueueboosts</id>
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<updated>2020-06-22T12:27:54Z</updated>
<entry>
<title>Change tsc_get_timecount return from uint to u_int per sys/timetc.h.</title>
<updated>2020-06-22T12:27:54Z</updated>
<author>
<name>pirofti</name>
<email>pirofti@openbsd.org</email>
</author>
<published>2020-06-22T12:27:54Z</published>
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<id>urn:sha1:b373bb1f2d041705cea84aa6125dc7f4c4ceae99</id>
<content type='text'>
First brought up by naddy@ in the usertc thread, OK kettenis@.
</content>
</entry>
<entry>
<title>fold the TSC value in fewer operations, same result; ok deraadt@</title>
<updated>2020-06-19T15:00:45Z</updated>
<author>
<name>naddy</name>
<email>naddy@openbsd.org</email>
</author>
<published>2020-06-19T15:00:45Z</published>
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<id>urn:sha1:ec4ed3a25fb7ac5b9c5a9ed6b8e4afed25159ea3</id>
<content type='text'>
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<entry>
<title>pci_intr_establish_cpu() for establishing an interrupt no a specific cpu.</title>
<updated>2020-06-17T06:14:52Z</updated>
<author>
<name>dlg</name>
<email>dlg@openbsd.org</email>
</author>
<published>2020-06-17T06:14:52Z</published>
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<id>urn:sha1:15db3095c63a1a68b250e90fee88dec8bf7f637d</id>
<content type='text'>
the cpu is specified by a struct cpu_info *, which should generally
come from an intrmap.

this is adapted from a diff that patrick@ sent round a few years
ago for a pci_intr_map_msix_cpuid, where you asked for an msi vector
on a specific cpu, and then called pci_intr_establish with the
handle you get. kettenis pointed out that it's hard on some archs
to carry cpu on a pci interrupt handle, so i tweaked it to turn it
into a pci_intr_establish_cpu instead.

jmatthew@ and i (but mostly jmatthew@ to be honest) have been
experimenting with this api on multiple archs and it is working out
well. i'm putting this diff in now on amd64 so people can kick the
tyres a bit.

tested with hacked up vmx(4), ix(4), and mcx(4)
</content>
</entry>
<entry>
<title>make intr_barrier run sched_barrier on the cpu the interrupt pinned to.</title>
<updated>2020-06-16T23:35:10Z</updated>
<author>
<name>dlg</name>
<email>dlg@openbsd.org</email>
</author>
<published>2020-06-16T23:35:10Z</published>
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<id>urn:sha1:25a8a2823803742cd59c645fe1cc4232a405aa64</id>
<content type='text'>
intr_barrier passed NULL to sched_barrier before this, which ends
up being the primary cpu. that's been mostly right until this point,
but is set to change.
</content>
</entry>
<entry>
<title>Check rdrand for success and try up to ten times, as recommended by Intel.</title>
<updated>2020-06-15T19:25:16Z</updated>
<author>
<name>naddy</name>
<email>naddy@openbsd.org</email>
</author>
<published>2020-06-15T19:25:16Z</published>
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<id>urn:sha1:dd423e202033ea6a7a2ccc1435d3d86866bb60c5</id>
<content type='text'>
Do the same for rdseed.
ok deraadt@
</content>
</entry>
<entry>
<title>crank version number</title>
<updated>2020-06-14T16:06:25Z</updated>
<author>
<name>deraadt</name>
<email>deraadt@openbsd.org</email>
</author>
<published>2020-06-14T16:06:25Z</published>
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<id>urn:sha1:29c02c14e09366e368ddf37ede6a9862fbfa2d6b</id>
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</entry>
<entry>
<title>asm versions of mdrandom() no longer needed</title>
<updated>2020-06-14T16:04:54Z</updated>
<author>
<name>deraadt</name>
<email>deraadt@openbsd.org</email>
</author>
<published>2020-06-14T16:04:54Z</published>
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<id>urn:sha1:0ddce9b0f2fc6f6888445b201113be717de0ac28</id>
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<entry>
<title>rewrite mdrandom() in C.  previously this XOR'd against rdrand if available,</title>
<updated>2020-06-14T16:00:08Z</updated>
<author>
<name>deraadt</name>
<email>deraadt@openbsd.org</email>
</author>
<published>2020-06-14T16:00:08Z</published>
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<id>urn:sha1:55f8664c3cb6c3d3b4f4fd806d3cc0a0106e6ba9</id>
<content type='text'>
and alternatively XOR'd against TSC.  now always run both sequences, and
also support rdseed as a third procedure.
ok kettenis naddy
</content>
</entry>
<entry>
<title>update drm to linux 5.7</title>
<updated>2020-06-08T04:47:57Z</updated>
<author>
<name>jsg</name>
<email>jsg@openbsd.org</email>
</author>
<published>2020-06-08T04:47:57Z</published>
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<id>urn:sha1:c349dbc7938c71a30e13c1be4acc1976165f4630</id>
<content type='text'>
adds kernel support for
amdgpu:		vega20, raven2, renoir, navi10, navi14
inteldrm:	icelake, tigerlake

Thanks to the OpenBSD Foundation for sponsoring this work, kettenis@ for
helping, patrick@ for helping adapt rockchip drm and many developers for
testing.
</content>
</entry>
<entry>
<title>let the random subsystem read the tsc for event "timestamps".</title>
<updated>2020-06-03T06:54:04Z</updated>
<author>
<name>dlg</name>
<email>dlg@openbsd.org</email>
</author>
<published>2020-06-03T06:54:04Z</published>
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