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<title>wireguard-openbsd/sys/arch/arm/cortex/cortex.c, branch jd/queueboosts</title>
<subtitle>WireGuard implementation for the OpenBSD kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-openbsd/atom/sys/arch/arm/cortex/cortex.c?h=jd%2Fqueueboosts</id>
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<updated>2020-04-29T15:25:07Z</updated>
<entry>
<title>Let the armv7 bus_dma layer and simplebus(4) implementation deal with</title>
<updated>2020-04-29T15:25:07Z</updated>
<author>
<name>kettenis</name>
<email>kettenis@openbsd.org</email>
</author>
<published>2020-04-29T15:25:07Z</published>
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<id>urn:sha1:37084e1e34e6eafe959b14d27c905d6c5ddf0888</id>
<content type='text'>
DMA remapping in the same way as arm64.  This relies on the dma-ranges
property in the device tree and allows us to get rid of the hack for
the Raspberry Pi in the dwctwo(4) driver.

Note that this does not include the hack in simplebus(4) that we have on
arm64 since firmware that has the dma-ranges is in widespread use now.

ok patrick@
</content>
</entry>
<entry>
<title>Rework mainbus and implement simplebus to be able to span a tree-like</title>
<updated>2016-05-02T08:15:55Z</updated>
<author>
<name>patrick</name>
<email>patrick@openbsd.org</email>
</author>
<published>2016-05-02T08:15:55Z</published>
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<id>urn:sha1:79645871eb1e6339dad244f36daa1838753bfcfb</id>
<content type='text'>
topology based on device tree information.  Introduce a common attach
args structure to be used for all fdt-capable bus devices.

ok jsg@ kettenis@
</content>
</entry>
<entry>
<title>Fix match function so that the cortex bus only attaches if the attach</title>
<updated>2016-04-08T12:08:54Z</updated>
<author>
<name>patrick</name>
<email>patrick@openbsd.org</email>
</author>
<published>2016-04-08T12:08:54Z</published>
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<id>urn:sha1:72d97272bbf56767c4175021e91f1447751e90f6</id>
<content type='text'>
args are actually looking for the cortex bus.

ok kettenis@
</content>
</entry>
<entry>
<title>add some more cortex A ids</title>
<updated>2015-05-29T05:48:07Z</updated>
<author>
<name>jsg</name>
<email>jsg@openbsd.org</email>
</author>
<published>2015-05-29T05:48:07Z</published>
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<id>urn:sha1:4ccb67867061257d1a4fb5304775c81241a3eee4</id>
<content type='text'>
</content>
</entry>
<entry>
<title>The Cortex bus should be useful for Cortex-A7, too.</title>
<updated>2013-08-06T14:21:13Z</updated>
<author>
<name>patrick</name>
<email>patrick@openbsd.org</email>
</author>
<published>2013-08-06T14:21:13Z</published>
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<id>urn:sha1:8ff1d18e94b02421c6ff162736c168a416ba16f6</id>
<content type='text'>
ok rapha@ jsg@
</content>
</entry>
<entry>
<title>Add a cortex bus which represents the ARM MPCore Complex.</title>
<updated>2013-05-01T00:16:26Z</updated>
<author>
<name>patrick</name>
<email>patrick@openbsd.org</email>
</author>
<published>2013-05-01T00:16:26Z</published>
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<id>urn:sha1:027018ef4d914bb0b556abc9782cb3f8de4ac6e4</id>
<content type='text'>
It will attach only to ARM Cortex A9 and A15 SoCs.
The generic interrupt controller and timer will attach to this bus,
later a secondary cache controller can be added.
The base address for those controllers are figured out using
the periphbase register.

ok bmercer@
</content>
</entry>
</feed>
