wireguard-openbsd/sys/arch/arm/cortex/cortex.h, branch jd/queueboosts WireGuard implementation for the OpenBSD kernel https://git.zx2c4.com/wireguard-openbsd/atom/sys/arch/arm/cortex/cortex.h?h=jd%2Fqueueboosts 2013-05-01T00:16:26Z Add a cortex bus which represents the ARM MPCore Complex. 2013-05-01T00:16:26Z patrick patrick@openbsd.org 2013-05-01T00:16:26Z urn:sha1:027018ef4d914bb0b556abc9782cb3f8de4ac6e4 It will attach only to ARM Cortex A9 and A15 SoCs. The generic interrupt controller and timer will attach to this bus, later a secondary cache controller can be added. The base address for those controllers are figured out using the periphbase register. ok bmercer@