wireguard-openbsd/sys/arch/arm/cortex/files.cortex, branch jd/queueboostsWireGuard implementation for the OpenBSD kernelhttps://git.zx2c4.com/wireguard-openbsd/atom/sys/arch/arm/cortex/files.cortex?h=jd%2Fqueueboosts2018-07-09T09:51:43ZImplement ampintcmsi(4) in ampintc(4) to support MSI. The GICv2M is an2018-07-09T09:51:43Zpatrickpatrick@openbsd.org2018-07-09T09:51:43Zurn:sha1:23a4b6369a213af2f82d67a0b843b4e939ee1a81
extension to the GIC controller, which is represented as subnode in the
device tree. There can be multiple GICv2Ms, so it makes sense to attach
those to ampintc(4) as some kind of simplebus. The GICv2M is simply an
interrupt generator that can be used by PCIe devices to ring the door
bell. There is no need for further configuration, we only need to find
out which SPIs we are allowed to use for MSI and to register an edge
triggered interrupt on a (randomly) allocated SPI.
Implement support for interrupt types. The GIC only seems to support
level triggered active-high or egdge triggered low-to-high interrupts.
We currently always configure them to be level triggered, which is a
sane default for most controllers. Since MSI interupts on the GIC are
edge triggered, we need to be able to parse the type information and to
configure the interrupt correspondingly.
ok kettenis@
Dynamically attach agtimer(4). Since agtimer(4) also provides the delay()2016-08-10T06:51:57Zketteniskettenis@openbsd.org2016-08-10T06:51:57Zurn:sha1:24e5cb751a4799c7949b6c79b6c5e543ab2e0a02
function for platforms that have it, rework the code a bit such that it can
be used before agtimer(4) attaches. Introduce a new agtimer_init()
function that checks whether the CPU implements the Generic Timer feature
and switches to agtimer_delay() if that feature is present. Call this
function from the generic platform initialization code.
ok jsg@
Dynamically attach ampintc(4) and make it register itself as an interrupt2016-08-04T15:52:52Zketteniskettenis@openbsd.org2016-08-04T15:52:52Zurn:sha1:6fc522b170aec3f74aa118c9c88b931d30a95f59
controller. Switch all i.MX6 devices over to the new FDT-aware interrupt
establish API and enable imxgpc(4).
This may break other platforms that use ampintc(4) as their interrupt
controller. We will fix this as soon as possible by switching them over
to the new interrupt establish API as well.
This also removes the hack in fec(4) to avoid the gpio-based interrupt
workaround. This commit is an essential step on the road to fix that
issue properly.
ok patrick@, jsg@
Rework mainbus and implement simplebus to be able to span a tree-like2016-05-02T08:15:55Zpatrickpatrick@openbsd.org2016-05-02T08:15:55Zurn:sha1:79645871eb1e6339dad244f36daa1838753bfcfb
topology based on device tree information. Introduce a common attach
args structure to be used for all fdt-capable bus devices.
ok jsg@ kettenis@
Support for the ARM Generic Timer used in the Cortex-A7 and Cortex-A15.2013-09-09T14:31:54Zpatrickpatrick@openbsd.org2013-09-09T14:31:54Zurn:sha1:466195a277a68cfb1e4d8827c4d8e5dd7e1330f0Add a driver for the secondary cache controller on the PandaBoard and2013-05-02T19:15:53Zpatrickpatrick@openbsd.org2013-05-02T19:15:53Zurn:sha1:d1433e4ad9bae9aa02aef97743bfd6ee09c39f96
other ARM Cortex based boards. Disabled for now, until proper
secondary cache flushing is done where it's needed.
ok miod@
Add a cortex bus which represents the ARM MPCore Complex.2013-05-01T00:16:26Zpatrickpatrick@openbsd.org2013-05-01T00:16:26Zurn:sha1:027018ef4d914bb0b556abc9782cb3f8de4ac6e4
It will attach only to ARM Cortex A9 and A15 SoCs.
The generic interrupt controller and timer will attach to this bus,
later a secondary cache controller can be added.
The base address for those controllers are figured out using
the periphbase register.
ok bmercer@