wireguard-openbsd/sys/arch/arm/cortex, branch jd/queueboosts

Let the armv7 bus_dma layer and simplebus(4) implementation deal with

2020-04-29T15:25:07Z

DMA remapping in the same way as arm64. This relies on the dma-ranges property in the device tree and allows us to get rid of the hack for the Raspberry Pi in the dwctwo(4) driver. Note that this does not include the hack in simplebus(4) that we have on arm64 since firmware that has the dma-ranges is in widespread use now. ok patrick@

Add IPI support. Taken ftrom arm64.

2019-09-29T10:36:52Z

ok patrick@

Enable interrupts while running interrupt handlers like we do on arm64.

2019-09-25T09:21:49Z

ok patrick@, jsg@

Make the code that calculates the min/max priorities identical to the arm64

2019-09-22T19:13:45Z

version. The divergence was probably an accident and the arm64 code makes more sense and is better tested. ok patrick@

Reduce diffs to arm64 version of this. Mostly whitespace changes.

2019-09-22T15:17:03Z

No functional changes.

For shared interrupts we need to make sure that we register

2018-12-07T21:33:28Z

with the lowest IPL. Once we actually run the IRQ handler we raise to the highest IPL. Fixes a crash seen when having a network card in the PCIe slot of the MacchiatoBin. ok ccardenas@

Use MAXCPUS as the number of elements for the array of per-cpu data.

2018-08-11T10:42:42Z

ok jsg@, patrick@

Make it possible to build a MULTIPROCESSOR kernel on armv7. While this

2018-08-06T18:39:13Z

doesn't actually spin up any secondary CPUs, it does run. Mostly a cleanup of along the lines of what I did earlier on arm64. Makes armv7 use the MI mplock implementation and implements copyin32. ok patrick@

Implement ampintcmsi(4) in ampintc(4) to support MSI. The GICv2M is an

2018-07-09T09:51:43Z

extension to the GIC controller, which is represented as subnode in the device tree. There can be multiple GICv2Ms, so it makes sense to attach those to ampintc(4) as some kind of simplebus. The GICv2M is simply an interrupt generator that can be used by PCIe devices to ring the door bell. There is no need for further configuration, we only need to find out which SPIs we are allowed to use for MSI and to register an edge triggered interrupt on a (randomly) allocated SPI. Implement support for interrupt types. The GIC only seems to support level triggered active-high or egdge triggered low-to-high interrupts. We currently always configure them to be level triggered, which is a sane default for most controllers. Since MSI interupts on the GIC are edge triggered, we need to be able to parse the type information and to configure the interrupt correspondingly. ok kettenis@

Rename Debugger() into db_enter().

2017-04-30T16:45:45Z

Using a name with the 'db_' prefix makes it invisible from the dynamic profiler. ok deraadt@, kettenis@, visa@