wireguard-openbsd/sys/arch/arm64/include, branch jd/queueboosts WireGuard implementation for the OpenBSD kernel https://git.zx2c4.com/wireguard-openbsd/atom/sys/arch/arm64/include?h=jd%2Fqueueboosts 2020-06-05T23:16:24Z Implement cpu_rnd_messybits() as a read of the virtual counter xored 2020-06-05T23:16:24Z naddy naddy@openbsd.org 2020-06-05T23:16:24Z urn:sha1:8274f7016bafdaa9664a02c123f04607750edbe0 with a bit-reversed copy of itself. There is progressively less entropy in the higher bits of a counter than in the lower bits, so bit-reverse one half in order to extract maximal entropy. style fixes and ok kettenis@ Allow userland access to the virtual counter. 2020-06-05T22:14:25Z kettenis kettenis@openbsd.org 2020-06-05T22:14:25Z urn:sha1:b0e77709c0dd5e58378837906c8281d687b7a4d8 ok patrick@, deraadt@ introduce "cpu_rnd_messybits" for use instead of nanotime in dev/rnd.c. 2020-05-31T06:23:56Z dlg dlg@openbsd.org 2020-05-31T06:23:56Z urn:sha1:01802d2cc63d886227ab3b39e923ff13cf516166 rnd.c uses nanotime to get access to some bits that change quickly between events that it can mix into the entropy pool. it doesn't use nanotime to get a monotonically increasing set or ordered and accurate timestamps, it just wants something with bits that change. there's been discussions for years about letting rnd use a clock that's super fast to read, but not necessarily accurate, but it wasn't until recently that i figured out it wasn't interested in time at all, so things like keeping a fast clock coherent between cpu cores or correct according to ntp is unecessary. this means we can just let rnd read the cycle counters on cpus and things will be fine. cpus with cycle counters that vary in their speed and arent kept consistent between cores may even be desirable in this context. so this is the first step in converting rnd.c to reading cycle counter. it copies the nanotime backend to each arch, and they can replace it with something MD as a second step later on. djm@ suggested rnd_messybytes, but we landed on cpu_rnd_messybits. thanks to visa for his eyes. ok deraadt@ visa@ deraadt@ says he will help handle any MD fallout that occurs. Fix typo in comment. 2020-05-17T13:36:33Z kettenis kettenis@openbsd.org 2020-05-17T13:36:33Z urn:sha1:f8c21047e63df663d400f96c8a1bf49ec52bdfa2 Add machdep.compatible. 2020-05-17T11:05:15Z kettenis kettenis@openbsd.org 2020-05-17T11:05:15Z urn:sha1:943434f8be7bd40574537218daf09c4f07eafc22 ok jsg@ Fix some of the more esoteric bus_space functions. The 2020-04-13T21:34:54Z kettenis kettenis@openbsd.org 2020-04-13T21:34:54Z urn:sha1:20d3e1cb58e574bc4b60f23a1d49160287788b1c bus_space_read_region_n, bus_space_write_region_n and bus_space_set_region_n functions were all broken. Fixes mvneta(4) on arm64. ok patrick@ controler -> controller 2020-02-20T06:12:14Z jsg jsg@openbsd.org 2020-02-20T06:12:14Z urn:sha1:29aa4a0f82304f8cea18befd646e6282fb5374ff Convert db_addr_t -> vaddr_t but leave the typedef for now. 2019-11-07T14:44:52Z mpi mpi@openbsd.org 2019-11-07T14:44:52Z urn:sha1:6d6b8a876ccc0691e0769b505db074d6e7d968ef Cache flush operations on arm64 were being incorrectly treated as write 2019-10-17T15:38:56Z drahn drahn@openbsd.org 2019-10-17T15:38:56Z urn:sha1:763137fc5fd00cb09a2ce6e4658fa5b68e986c35 operations, however they should be treated as read per the design. Switch to using bit defines, correct said defines. Fixes cache flushing causing Firefox to abort. ok kettenis@ kurt@ Newer ARMv8 processors now include a new CSV2 field in their processor 2019-09-01T15:34:15Z kettenis kettenis@openbsd.org 2019-09-01T15:34:15Z urn:sha1:53458e9799858478faaea3fe0c79718f5a8122d9 feature register that can indicate that a processor is not vulnarable to Spectre v2 attacks. Use this field in favour of adding specific processors to a whitelist. Continue to whitelist the few processors that are known not to be vulnerable but don't set the appropriate value in the CSV2 field. ok jsg@