WireGuard implementation for the OpenBSD kernel https://git.zx2c4.com/wireguard-openbsd/atom/sys/arch/arm64/include?h=master 2021-03-27T20:03:15Z 2021-03-27T20:03:15Z kettenis kettenis@openbsd.org 2021-03-27T20:03:15Z urn:sha1:9125e0069c7db1eefdb073f443c9bcc88e5de219 Do this by clearing all the bits marked RES0 and set all the bits marked RES1 for the ARMv8.0. Any optional features introduced in later revisions of the architecture (such as PAN) will be enabled after SCTLR_EL1 is initialized. ok patrick@ 2021-03-27T19:57:19Z kettenis kettenis@openbsd.org 2021-03-27T19:57:19Z urn:sha1:e9875c8fb27bdee9bc60930a50dd3845ddc5875c ok patrick@ 2021-03-22T20:30:21Z patrick patrick@openbsd.org 2021-03-22T20:30:21Z urn:sha1:cc0ede0677b0110958241fb25b9e05031b91a387 typically pass the physical address, however retrieved, to our PCIe controller code. This physical address can in practise be directly given to the PCIe, but it is not a given that the CPU and the PCIe controller are able to use the same physical addresses. This is even more obvious with an smmu(4) inbetween, which can change the world view by introducing I/O virtual addresses. Hence for this it is indeed necessary to map those pages, which thanks to integration with bus_dma(9) works easily. For this we remember the PCI devices' DMA tag in the interrupt handle during the MSI map, so that we can use the smmu(4)-hooked DMA tag to load the physical address. While some systems might prefer to implement "trapping" pages for MSIs, to make sure devices cannot trigger other devices' interrupts, we only make sure the whole page is mapped. Having the IOMMU create a mapping for each MSI is a bit wasteful, but for now it's the simplest way to implement it. Discussed with and ok kettenis@ 2021-03-11T11:16:54Z jsg jsg@openbsd.org 2021-03-11T11:16:54Z urn:sha1:36fd90dcf1acf2ddb4ef5dbabe5313b3a8d46ee2 2021-03-08T11:16:26Z kettenis kettenis@openbsd.org 2021-03-08T11:16:26Z urn:sha1:c6c0d427aa8cbc6b33fafa1efea112f5ce5aaa30 ASIDs. This should only happen on systems with 8-bit ASIDs, which are currently unsupported in OpenBSD. The new scheme uses "generations". Whenever we run out of ASIDs we bump the generation and flush the complete TLB. The pmaps of processes that are currently on the CPU are carried over into the new generation. This implementation relies on the scheduler lock to make sure this happens without any (known) races. ok patrick@, mpi@ 2021-02-28T21:28:33Z patrick patrick@openbsd.org 2021-02-28T21:28:33Z urn:sha1:f8ea3ffd3a00c874670c733f9c5b67a13b8890ae ok kettenis@ 2021-02-25T23:07:48Z patrick patrick@openbsd.org 2021-02-25T23:07:48Z urn:sha1:619b146d99f441b1442881c022ac42665e3f35f6 so that we can provide IOMMU-hooked bus DMA tags for each PCI device. ok kettenis@ 2021-02-23T10:20:10Z jsg jsg@openbsd.org 2021-02-23T10:20:10Z urn:sha1:2e4f0d95aeae5f7c52ca7e76b88e9df56a856c15 2021-02-21T13:14:47Z kettenis kettenis@openbsd.org 2021-02-21T13:14:47Z urn:sha1:5fc49d225758d1768cbaca44e5e75a0bf9c4c905 running the kernel in EL2. ok patrick@ 2021-02-17T12:11:44Z kettenis kettenis@openbsd.org 2021-02-17T12:11:44Z urn:sha1:adc7c282072bd0a8067bf9fbcf42318cb4ad7921 since its interrupts seem to be hardwared to trigger an FIQ instead of an IRQ. This means we need to manipulate both the F and the I bit in the DAIF register when enabling and disabling interrupts. ok patrick@