wireguard-openbsd/sys/arch/arm64, branch master WireGuard implementation for the OpenBSD kernel https://git.zx2c4.com/wireguard-openbsd/atom/sys/arch/arm64?h=master 2021-04-03T15:59:08Z Add a guard page between I/O virtual address space allocations. The idea 2021-04-03T15:59:08Z patrick patrick@openbsd.org 2021-04-03T15:59:08Z urn:sha1:a5eb7f55b9c1dc179deb7da5fa31c6889c73c8ca is that IOVA allocations always have a gap in-between which produces a fault on access. If a transfer to a given allocation runs further than expected we should be able to see it. We pre-allocate IOVA on bus DMA map creation, and as long as we don't allocate a PTE descriptor, this comes with no cost. We have plenty of address space anyway, so adding a page-sized gap does not hurt at all and can only have positive effects. Idea from kettenis@ Exclude the first page from I/O virtual address space, which is the NULL 2021-04-03T15:10:58Z patrick patrick@openbsd.org 2021-04-03T15:10:58Z urn:sha1:ab86b9020dc7a7e0f5e6f0a183513a03d13d2e53 pointer address. Not allowing this one to be allocated might help find driver bugs, where the device is programmed with a NULL pointer. We have plenty of address space anyway, so excluding this single page does not hurt at all and can only have positive effects. Idea from kettenis@ Fix Dale's email address 2021-04-02T03:02:45Z tb tb@openbsd.org 2021-04-02T03:02:45Z urn:sha1:1e299ff15b043b3abdc6f76f4191ab07b19228c1 ok drahn Turns out the PCIe DARTs support a full 32-bit device virtual address space. 2021-03-29T17:04:00Z kettenis kettenis@openbsd.org 2021-03-29T17:04:00Z urn:sha1:14edd68e6a4948d2244829bbd092d21a09e8127c Adjust the region managed by the extend accordingly but avoid the first and last page. The last page collides with the MSI address used by the PCIe controller and not using the first page helps finding bugs. ok patrick@ Make sure that all CPUs end up with the same bits set in SCTLR_EL1. 2021-03-27T20:03:15Z kettenis kettenis@openbsd.org 2021-03-27T20:03:15Z urn:sha1:9125e0069c7db1eefdb073f443c9bcc88e5de219 Do this by clearing all the bits marked RES0 and set all the bits marked RES1 for the ARMv8.0. Any optional features introduced in later revisions of the architecture (such as PAN) will be enabled after SCTLR_EL1 is initialized. ok patrick@ Add ARMv8.5 instruction set related CPU features. 2021-03-27T19:57:19Z kettenis kettenis@openbsd.org 2021-03-27T19:57:19Z urn:sha1:e9875c8fb27bdee9bc60930a50dd3845ddc5875c ok patrick@ Fix "mach dtb" return code to avoid bogus boot 2021-03-26T23:29:21Z kn kn@openbsd.org 2021-03-26T23:29:21Z urn:sha1:fcf3d43cc0b90d9e05a8e1269932955a1857612c Bootloader command functions must return zero in case of failure, returning 1 tells the bootloader to boot the currently set kernel iamge. "machine dtb" is is the wrong way around so using it triggers a boot. Fix this and print a brief usage (like other commands such as "hexdump" do) while here. Feedback OK patrick Fix errno, merge ioctl cases 2021-03-26T22:55:48Z kn kn@openbsd.org 2021-03-26T22:55:48Z urn:sha1:def7dd08d0e32b362027b34be550101a5e9795f4 The EBADF error is always overwritten for the standby, suspend and hibernate ioctls, only the mode ioctl has it right. Merge the now identical casese while here. OK patrick Pack the SPCR struct definition since the struct isn't naturally aligned 2021-03-23T09:41:12Z patrick patrick@openbsd.org 2021-03-23T09:41:12Z urn:sha1:eeb8d4725bb547b9e48e7cf690b06be1f2f06587 or padded, and hence e. g. the access to the PCI vendor/device id would be broken. The structs for the other tables all seem to be packed as well. ok kettenis@ Now that MSI pages are properly mapped, all that debug code in smmu(4) 2021-03-22T20:34:45Z patrick patrick@openbsd.org 2021-03-22T20:34:45Z urn:sha1:a66e8666dd1e8617ff67e2f516e578445287310a can be removed. The only thing left to implement for smmu(4) to work out of the box with PCIe devices is to reserve the PCIe MMIO windows. Let's see how we can do this properly.