wireguard-openbsd/sys/arch/mips64/include/asm.h, branch jd/queueboosts

Rely on the hardware to clear hazards on octeon.

2017-08-27T04:32:29Z

kill RCSID macros; discussed with millert

2017-06-29T17:36:16Z

Add _MIPS_ISA_MIPS32 and _MIPS_ISA_MIPS64 defines for clang.

2017-01-21T14:45:29Z

OK deraadt@ phessler@ mpi@

After reading IRIX header files again, add one more SSNOP to MTC0_HAZARD (and

2015-09-21T21:22:44Z

remove one from constructs based upon it) when building for R8000.

Revert previous; turns out to be necessary to build the 32-bit boot blocks

2014-03-14T16:57:21Z

on sgi.

remove #if(n)def LP64 from the mips64 codebase, as mips32 never really went anywhere.

2014-03-11T07:50:49Z

ok miod@

Add STRONG_ALIAS macros to be used from assembly code in libc and

2013-03-28T17:41:03Z

libm. While at it, remove now unused workarounds for lint. Agreed by kettenis@, guenther@, matthew@.

Basic R8000 processor support. R8000 processors require MMU-specific code,

2012-09-29T21:37:01Z

exception-specific code, clock-specific code, and L1 cache-specific code. L2 cache is per-design, of which only two exist: SGI Power Indigo2 (IP26) and SGI Power Challenge (IP21) and are not covered by this commit. R8000 processors also are 64-bit only processors with 64-bit coprocessor 0 registers, and lack so-called ``compatibility'' memory spaces allowing 32-bit code to run with sign-extended addresses and registers. The intrusive changes are covered by #ifdef CPU_R8000 stanzas. However, trap() is split into a high-level wrapper and a new function, itsa(), responsible for the actual trap servicing (which name couldn't be helped because I'm an incorrigible punster). While an R8000 exception may cause (via trap() ) multiple exceptions to be serviced, non-R8000 processors will always service one exception in trap(), but they are nevertheless affected by this code split.

Introduce assembly macros for specific processor hazards: tlb update, status

2012-09-29T19:02:25Z

register update, status register update causing a change to the interrupt enable flag, and a few other arcane ones. will provide (supposedly sane) defaults, and may override these with better tuned versions. Use these macros instead of random strings of nop in the various .S files requiring hazard workarounds.

Provide a few more macros in to wrap coprocessor 0

2012-09-29T18:56:23Z

move from/to register instructions, as well as a NOP macro. These will be used in a later diff to allow specific processors to use slightly different instructions or encodings.