wireguard-openbsd/sys/arch/mips64/include/cache.h, branch jd/queueboosts

Add a driver for OCTEON MMC host controller.

2016-12-21T13:59:57Z

Tested on EdgeRouter Pro, and Shasta. OK mpi@

Some implementations of HitSyncDCache() call pmap_extract() for va->pa

2016-01-05T05:27:54Z

conversion. Because pmap_extract() acquires the PTE mutex, a "locking against myself" panic is triggered if the cache routine gets called in a context where the mutex is already held. In the pmap, all calls to HitSyncDCache() are for a whole page. Add a new cache routine, HitSyncDCachePage(), which gets both the va and the pa of a page. This removes the need of the va->pa conversion. The new routine has the same signature as SyncDCachePage(), allowing reuse of the same routine for cache implementations that do not need differences between "Hit" and non-"Hit" routines. With the diff, POWER Indigo2 R8000 boots multiuser again. Tested on sgi GENERIC-IP27.MP and octeon GENERIC.MP, too. Diff from miod@, ok kettenis@

Some bits for Loongson 3A support.

2015-08-15T22:31:38Z

Due the virtually indexed nature of the L1 instruction cache on most mips

2014-03-31T20:21:18Z

processors, every time a new text page is mapped in a pmap, the L1 I$ is flushed for the va spanned by this page. Since we map pages of our binaries upon demand, as they get faulted in, but uvm_fault() tries to map the few neighbour pages, this can end up in a bunch of pmap_enter() calls in a row, for executable mappings. If the L1 I$ is small enough, this can cause the whole L1 I$ cache to be flushed several times. Change pmap_enter() to postpone these flushes by only registering the pending flushes, and have pmap_update() perform them. The cpu-specific cache code can then optimize this to avoid unnecessary operations. Tested on R4000SC, R4600SC, R5000SC, RM7000, R10000 with 4KB and 16KB page sizes (coherent and non-coherent designs), and Loongson 2F by mikeb@ and me. Should not affect anything on Octeon since there is no way to flush a subset of I$ anyway.

Basic R8000 processor support. R8000 processors require MMU-specific code,

2012-09-29T21:37:01Z

exception-specific code, clock-specific code, and L1 cache-specific code. L2 cache is per-design, of which only two exist: SGI Power Indigo2 (IP26) and SGI Power Challenge (IP21) and are not covered by this commit. R8000 processors also are 64-bit only processors with 64-bit coprocessor 0 registers, and lack so-called ``compatibility'' memory spaces allowing 32-bit code to run with sign-extended addresses and registers. The intrusive changes are covered by #ifdef CPU_R8000 stanzas. However, trap() is split into a high-level wrapper and a new function, itsa(), responsible for the actual trap servicing (which name couldn't be helped because I'm an incorrigible punster). While an R8000 exception may cause (via trap() ) multiple exceptions to be serviced, non-R8000 processors will always service one exception in trap(), but they are nevertheless affected by this code split.

Do not output unnecessary semicolons when expanding macros. No functional change

2012-06-24T20:20:37Z

Rework the signature of the cache handling routines again. It makes more sense

2012-04-21T12:20:30Z

to pass both the virtual and physical addresses of the page to clean to SyncDCachePage, which is the only routine using `Index' operations on the data cache, which might be virtually indexed at some levels but physically indexed at others. On the other hand, it does not make any sense to pass a physical address to routines using `Hit' operations (and they were discarding them anyway). In addition to making things cleaner, this fixes sporadic userland misbehaviour (read: SIGSGEV) on RM7000 O2 systems.

Make the logic for PMAP_PREFER() and the logic, inside pmap, to do the

2012-04-06T20:11:18Z

necessary cache coherency work wrt similar virtual indexes of different physical pages, depending upon two distinct global variables, instead of a shared one. R4000/R4400 VCE requires a 32KB mask for PMAP_PREFER, which is otherwise not necessary for pmap coherency (especially since, on these processors, only L1 uses virtual indexes, and the L1 size is not greater than the page size, as we are using 16KB pages).

Move cache handling routines related definitions to a dedicated header file,

2012-03-25T13:52:52Z

rather than abusing .