wireguard-openbsd/sys/arch/mips64/include/mips_opcode.h, branch jd/queueboosts WireGuard implementation for the OpenBSD kernel https://git.zx2c4.com/wireguard-openbsd/atom/sys/arch/mips64/include/mips_opcode.h?h=jd%2Fqueueboosts 2017-04-20T15:42:26Z Make TCB address available to userspace via the UserLocal register. 2017-04-20T15:42:26Z visa visa@openbsd.org 2017-04-20T15:42:26Z urn:sha1:2fef4a9239f881729bf148d7a57caa1ebe22d91f This lets programs get the address without a system call on OCTEON II and later. Add UserLocal load emulation for systems that do not implement the RDHWR instruction or the UserLocal register. OK guenther@ Basic R8000 processor support. R8000 processors require MMU-specific code, 2012-09-29T21:37:01Z miod miod@openbsd.org 2012-09-29T21:37:01Z urn:sha1:a4a4ed5c8cec53549246aa9dfdb1cf81ba631dd3 exception-specific code, clock-specific code, and L1 cache-specific code. L2 cache is per-design, of which only two exist: SGI Power Indigo2 (IP26) and SGI Power Challenge (IP21) and are not covered by this commit. R8000 processors also are 64-bit only processors with 64-bit coprocessor 0 registers, and lack so-called ``compatibility'' memory spaces allowing 32-bit code to run with sign-extended addresses and registers. The intrusive changes are covered by #ifdef CPU_R8000 stanzas. However, trap() is split into a high-level wrapper and a new function, itsa(), responsible for the actual trap servicing (which name couldn't be helped because I'm an incorrigible punster). While an R8000 exception may cause (via trap() ) multiple exceptions to be serviced, non-R8000 processors will always service one exception in trap(), but they are nevertheless affected by this code split. Correct a wrong comment. 2012-04-21T19:13:14Z miod miod@openbsd.org 2012-04-21T19:13:14Z urn:sha1:944cd5b7c5db0ad8d859e6a75158360845d827d5 Normalize sentinel. Use _MACHINE_*_H_ and _<ARCH>_*_H_ properly and consitently. 2011-03-23T16:54:33Z pirofti pirofti@openbsd.org 2011-03-23T16:54:33Z urn:sha1:2fa72412907ae78c4787a4a8f888c5f0486e225c Discussed and okay drahn@. Okay deraadt@. Overhaul ddb disassembler to recognize all MIPS IV instructions, as well as 2010-09-19T23:34:33Z miod miod@openbsd.org 2010-09-19T23:34:33Z urn:sha1:12a2e78e4f53baf587fc9f0b43eaab3a6ac9a4d2 some mips64r2 instructions. Various bugfixes all over as well (conditional trap instructions do not have a delay slot, for instance). Recognize MIPS IV extra FPU condition codes in MipsEmulateBranch(). 2010-09-17T00:36:30Z miod miod@openbsd.org 2010-09-17T00:36:30Z urn:sha1:bb80a8d65c6e819c8db3df67fd1db4612ad4c129 There is only one code for coprocessor BC opcodes, so don't bother to handle 2010-09-17T00:25:10Z miod miod@openbsd.org 2010-09-17T00:25:10Z urn:sha1:5680a77e4ccdc04a920417492b0db89148d15819 a second (invalid) opcode; confirmed by all mips core documentation. Remove advertising clause from UCB licenses; ok deraad@ 2005-08-07T07:29:44Z miod miod@openbsd.org 2005-08-07T07:29:44Z urn:sha1:53aa784a41578b06c923d9b3a5590acbd3bd0b73 initial mips64 2004-08-06T20:56:01Z pefo pefo@openbsd.org 2004-08-06T20:56:01Z urn:sha1:f58c7388c5899f6e305e403d642605f83ca7e919