<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-openbsd/sys/arch/mips64/include/trap.h, branch jd/queueboosts</title>
<subtitle>WireGuard implementation for the OpenBSD kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-openbsd/atom/sys/arch/mips64/include/trap.h?h=jd%2Fqueueboosts</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-openbsd/atom/sys/arch/mips64/include/trap.h?h=jd%2Fqueueboosts'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-openbsd/'/>
<updated>2014-04-09T21:10:34Z</updated>
<entry>
<title>Make trapDump() take the printf-like function as a 2nd parameter.</title>
<updated>2014-04-09T21:10:34Z</updated>
<author>
<name>miod</name>
<email>miod@openbsd.org</email>
</author>
<published>2014-04-09T21:10:34Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-openbsd/commit/?id=e4dd48157348a00abf16adb77a30a6475932633a'/>
<id>urn:sha1:e4dd48157348a00abf16adb77a30a6475932633a</id>
<content type='text'>
No functional change; helps non-released kernels with extra debugging code (-:
</content>
</entry>
<entry>
<title>Handle the coprocessor 0 cause and status registers as a 64 bit value now,</title>
<updated>2012-09-29T19:24:30Z</updated>
<author>
<name>miod</name>
<email>miod@openbsd.org</email>
</author>
<published>2012-09-29T19:24:30Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-openbsd/commit/?id=a6ba7b46603db6744f75f2fc54ec1ca7b92023b9'/>
<id>urn:sha1:a6ba7b46603db6744f75f2fc54ec1ca7b92023b9</id>
<content type='text'>
as some odd mips designs need moro than 32 bits in there. This causes a lot
of mechanical changes everywhere getsr() is used.
</content>
</entry>
<entry>
<title>Add a few more coprocessor 0 cause and config registers defines.</title>
<updated>2012-09-29T19:13:13Z</updated>
<author>
<name>miod</name>
<email>miod@openbsd.org</email>
</author>
<published>2012-09-29T19:13:13Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-openbsd/commit/?id=547c5d1da03a5d426d0ad49a6afa0819b33e8c22'/>
<id>urn:sha1:547c5d1da03a5d426d0ad49a6afa0819b33e8c22</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Normalize sentinel. Use _MACHINE_*_H_ and _&lt;ARCH&gt;_*_H_ properly and consitently.</title>
<updated>2011-03-23T16:54:33Z</updated>
<author>
<name>pirofti</name>
<email>pirofti@openbsd.org</email>
</author>
<published>2011-03-23T16:54:33Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-openbsd/commit/?id=2fa72412907ae78c4787a4a8f888c5f0486e225c'/>
<id>urn:sha1:2fa72412907ae78c4787a4a8f888c5f0486e225c</id>
<content type='text'>
Discussed and okay drahn@. Okay deraadt@.
</content>
</entry>
<entry>
<title>Make trapdebug code MP-safe.</title>
<updated>2010-01-18T16:57:44Z</updated>
<author>
<name>miod</name>
<email>miod@openbsd.org</email>
</author>
<published>2010-01-18T16:57:44Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-openbsd/commit/?id=2f07252997ae200946f0a94d3cae38f94990aa61'/>
<id>urn:sha1:2f07252997ae200946f0a94d3cae38f94990aa61</id>
<content type='text'>
</content>
</entry>
<entry>
<title>typo</title>
<updated>2009-11-12T19:45:53Z</updated>
<author>
<name>miod</name>
<email>miod@openbsd.org</email>
</author>
<published>2009-11-12T19:45:53Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-openbsd/commit/?id=5060888dfbb963e8ab3e9ffb6b0779a265cbe5b2'/>
<id>urn:sha1:5060888dfbb963e8ab3e9ffb6b0779a265cbe5b2</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Completely overhaul interrupt handling on sgi. Cpu state now only stores a</title>
<updated>2009-10-22T22:08:52Z</updated>
<author>
<name>miod</name>
<email>miod@openbsd.org</email>
</author>
<published>2009-10-22T22:08:52Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-openbsd/commit/?id=91b9a95c5768ded8b9c299978444d7f064ca56c5'/>
<id>urn:sha1:91b9a95c5768ded8b9c299978444d7f064ca56c5</id>
<content type='text'>
logical IPL level, and per-platform (IP27/IP30/IP32) code will from the
necessary hardware mask registers.

This allows the use of more than one interrupt mask register. Also, the
generic (platform independent) interrupt code shrinks a lot, and the actual
interrupt handler chains and masking information is now per-platform private
data.

Interrupt dispatching is generated from a template; more routines will be
added to the template to reduce platform-specific changes and share as much
code as possible.

Tested on IP27, IP30, IP32 and IP35.
</content>
</entry>
<entry>
<title>Add ``guarded'' word read and write routines, to be used by machine-dependent</title>
<updated>2008-04-07T22:37:16Z</updated>
<author>
<name>miod</name>
<email>miod@openbsd.org</email>
</author>
<published>2008-04-07T22:37:16Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-openbsd/commit/?id=73f158a316e271262be2a232311375f1afc0f184'/>
<id>urn:sha1:73f158a316e271262be2a232311375f1afc0f184</id>
<content type='text'>
code soon. Similar to what ddb does, but does not need ddb to be compiled in.
</content>
</entry>
<entry>
<title>Remove unused badaddr().</title>
<updated>2007-05-20T14:34:21Z</updated>
<author>
<name>miod</name>
<email>miod@openbsd.org</email>
</author>
<published>2007-05-20T14:34:21Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-openbsd/commit/?id=7025e1b27c3a8a30739933d1040b54a688085f17'/>
<id>urn:sha1:7025e1b27c3a8a30739933d1040b54a688085f17</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Define R5k/R10k extra trap codes.</title>
<updated>2006-06-06T17:42:28Z</updated>
<author>
<name>miod</name>
<email>miod@openbsd.org</email>
</author>
<published>2006-06-06T17:42:28Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-openbsd/commit/?id=130f257052ed6c9a515820ee4cccfd113c3f703c'/>
<id>urn:sha1:130f257052ed6c9a515820ee4cccfd113c3f703c</id>
<content type='text'>
</content>
</entry>
</feed>
