wireguard-openbsd/sys/arch/powerpc/include/cpu.h, branch jd/queueboosts WireGuard implementation for the OpenBSD kernel https://git.zx2c4.com/wireguard-openbsd/atom/sys/arch/powerpc/include/cpu.h?h=jd%2Fqueueboosts 2020-06-05T14:25:05Z Implement cpu_rnd_messybits() as a read of the cycle counter register. 2020-06-05T14:25:05Z naddy naddy@openbsd.org 2020-06-05T14:25:05Z urn:sha1:4f1155a8e1b8d56b62802304c62b79d4e918eb9a ok dlg@, powerpc/sparc64 ok kettenis@, sparc64/alpha tested by deraadt@ introduce "cpu_rnd_messybits" for use instead of nanotime in dev/rnd.c. 2020-05-31T06:23:56Z dlg dlg@openbsd.org 2020-05-31T06:23:56Z urn:sha1:01802d2cc63d886227ab3b39e923ff13cf516166 rnd.c uses nanotime to get access to some bits that change quickly between events that it can mix into the entropy pool. it doesn't use nanotime to get a monotonically increasing set or ordered and accurate timestamps, it just wants something with bits that change. there's been discussions for years about letting rnd use a clock that's super fast to read, but not necessarily accurate, but it wasn't until recently that i figured out it wasn't interested in time at all, so things like keeping a fast clock coherent between cpu cores or correct according to ntp is unecessary. this means we can just let rnd read the cycle counters on cpus and things will be fine. cpus with cycle counters that vary in their speed and arent kept consistent between cores may even be desirable in this context. so this is the first step in converting rnd.c to reading cycle counter. it copies the nanotime backend to each arch, and they can replace it with something MD as a second step later on. djm@ suggested rnd_messybytes, but we landed on cpu_rnd_messybits. thanks to visa for his eyes. ok deraadt@ visa@ deraadt@ says he will help handle any MD fallout that occurs. Fix inline assembly in ppc_mftb(); using %L0 instead of %0+1 makes this work 2020-03-17T10:14:45Z kettenis kettenis@openbsd.org 2020-03-17T10:14:45Z urn:sha1:1b5c1bb041a8716a4f9de2b79b9d94b5d3e53c6a for both gcc and clang. From NetBSD. Thanks to some serious detective work by ghoehler@. ok deraadt@, gkeohler@ Add intr_{disable,restore}() for powerpc. 2019-03-23T05:27:53Z visa visa@openbsd.org 2019-03-23T05:27:53Z urn:sha1:f803efbff0a45e217da2c5f5bdc57a47fc1931de OK mpi@ patrick@ Include srp.h where struct cpu_info uses srp to avoid erroring out when 2018-12-05T10:28:21Z jsg jsg@openbsd.org 2018-12-05T10:28:21Z urn:sha1:1a1181a966226532433438cb3741ae7cdc0727d4 including cpu.h machine/intr.h etc without first including param.h when MULTIPROCESSOR is defined. ok visa@ Flush page (through the direct map) before mapping it into AGP. Fixes 2016-05-07T22:46:54Z kettenis kettenis@openbsd.org 2016-05-07T22:46:54Z urn:sha1:a24104fb51fd861f7d242c4f28afab2e22cbf697 artifacts seen in X on some G5 machines. Unfortunately not enough to fix G4 machines. With help from Marcus Glocker. ok mpi@ introduce srp, which according to the manpage i wrote is short for 2015-07-02T01:33:59Z dlg dlg@openbsd.org 2015-07-02T01:33:59Z urn:sha1:52776b7dd171c092a35f86a9ed8bd1c22cac9fb8 "shared reference pointers". srp allows concurrent access to a data structure by multiple cpus while avoiding interlocking cpu opcodes. it manages its own reference counts and the garbage collection of those data structure to avoid use after frees. internally srp is a twisted version of hazard pointers, which are a relative of RCU. jmatthew wrote the bulk of a hazard pointer implementation and changed bpf to use it to allow mpsafe access to bpfilters. however, at s2k15 we were trying to apply it to other data structures but the memory overhead of every hazard pointer would have blown out significantly in several uses cases. a bulk of our time at s2k15 was spent reworking hazard pointers into srp. this diff adds the srp api and adds the necessary metadata to struct cpuinfo on our MP architectures. srp on uniprocessor platforms has alternate code that is optimised because it knows there'll be no concurrent access to data by multiple cpus. srp is made available to the system via param.h, so it should be available everywhere in the kernel. the docs likely need improvement cos im too close to the implementation. ok mpi@ Make it possisble to disable block address translation mechanism on 2015-03-31T16:00:38Z mpi mpi@openbsd.org 2015-03-31T16:00:38Z urn:sha1:5c8048c1d30761e2471fbfddb5e4847568d14a54 processors that support it. Due to the way trap code is patched it is currently not possible to enabled/disable BAT at runtime. ok miod@, kettenis@ no md code wants lockmgr locks, so no md code needs to include sys/lock.h 2015-02-11T07:05:39Z dlg dlg@openbsd.org 2015-02-11T07:05:39Z urn:sha1:d3b1d173f07835f2d78b379d23a5946ce16b055a with and ok miod@ Implement splassert(9) for powerpc. 2015-01-04T13:01:42Z mpi mpi@openbsd.org 2015-01-04T13:01:42Z urn:sha1:1c471f421f412895a8ccf0461fc716494b91bf1d This changes the logic to prevent a recursion when processing soft interrupts. Previously a per-CPU flag was set before re-enabling interrupts. Now the IPL level is raised to SOFTTTY which makes splsoftassert() happy, greatly inspired by mips64. As a side effect, the ppc_intr_{disable,enable}() dance is now done only once instead of twice per splx(9). While here, make use of dosoftint() instead of having 3 different functions for dispatching soft interrupts. Tested by deraadt@ on G4 smp and by myself G5 smp, G3, G4 and socppc. No objection from the usual (and over busy) suspects.