wireguard-openbsd/sys/arch/sgi/dev/power.c, branch jd/queueboosts WireGuard implementation for the OpenBSD kernel https://git.zx2c4.com/wireguard-openbsd/atom/sys/arch/sgi/dev/power.c?h=jd%2Fqueueboosts 2018-12-03T13:46:30Z Remove the unused interrupt type (edge/level) from the mace interrupt 2018-12-03T13:46:30Z visa visa@openbsd.org 2018-12-03T13:46:30Z urn:sha1:a68d5b24c038de22fdf4e4fd70d80d250bd50085 handler registration. The code is inherited from isa(4), but on the O2, although some interrupt sources on CRIME are edge-triggered, all the MACE interrupts are level-triggered. From miod@ It's init as a process that's special, not init's original thread. 2014-07-11T08:18:30Z guenther guenther@openbsd.org 2014-07-11T08:18:30Z urn:sha1:de4108ea246ca18ecf2b1c2da217fe05eaa13f68 Remember initprocess instead of initproc. ok matthew@ blambert@ machdep.kbdreset enables a shutdown by Ctrl-Alt-Del on amd64 and 2011-06-24T19:47:48Z naddy naddy@openbsd.org 2011-06-24T19:47:48Z urn:sha1:b2e0f490b253e780e76a918839034208349842cf i386. Stop abusing it on other archs for controling a shutdown by pressing the soft power button: * Add a MI sysctl hw.allowpowerdown; if set to 1 (the default) it allows a power button shutdown. * Make acpi(4)/acpibtn(4) honor hw.allowpowerdown. * Switch the various power button intercepts on landisk, sgi, sparc64 and zaurus over to hw.allowpowerdown. * Garbage collect the machdep.kbdreset sysctl on all archs other than amd64 and i386. ok miod@ Allow xbow_intr_establish() callers to provide optional storage for the 2009-11-25T11:23:29Z miod miod@openbsd.org 2009-11-25T11:23:29Z urn:sha1:7597b9cb5f634835addffa1528b7f6854f5d0623 struct intrhand, instead of having it malloc()'ed. Rename struct confargs to struct mainbus_attach_args for consistency and also 2009-10-26T20:14:40Z miod miod@openbsd.org 2009-10-26T20:14:40Z urn:sha1:a69e38b2415054b31b7a507da8e2da1738211d95 to prevent further abuse of it. Add support for the Octane power button to power(4). Took me a while to 2009-10-26T18:13:31Z miod miod@openbsd.org 2009-10-26T18:13:31Z urn:sha1:f4fb410de5d9ee41236648cafe8b8c42b67c7ff7 figure out how the interrupt was routed from xbridge to xheart... (it bypasses the regular `have xbridge send a xio interrupt packet' mechanism) Better crime/mace interrupt handling; interrupt information is no longer 2009-10-26T18:00:04Z miod miod@openbsd.org 2009-10-26T18:00:04Z urn:sha1:ed8baf6720d6283035f69809c73921c44aa0ddf6 specified in the kernel configuration file, but is provided by macebus(4) as part of the child device attachment args, and provide both crime and mace interrupt bitmasks; this allows us to only really enable interrupt sources we care about, and to avoid invoking interrupt handler we don't need to for the few mace interrupts multiplexed at the crime level. need that include file... 2009-05-16T16:04:11Z deraadt deraadt@openbsd.org 2009-05-16T16:04:11Z urn:sha1:d45421e79cc9001df91459af16b17dfd599fe557 TOD clock support for IOC3 flavours with DS174x chips (which are rebadged 2009-05-15T23:02:23Z miod miod@openbsd.org 2009-05-15T23:02:23Z urn:sha1:7ae2547e9c4fafce13182cc118195df432cd627f MK48Txx). Entangled with preliminary changes which will hopefully eventually lead to power(4) attaching on IP30 (but not finished yet). - remove some unneeded headers 2008-09-16T16:38:25Z jasper jasper@openbsd.org 2008-09-16T16:38:25Z urn:sha1:6cc76996971cb667c6d288e60b3b10af8345139c with and ok jsing@