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| author |   visa <visa@openbsd.org> | 2015-09-26 04:37:18 +0000 |
|---|---|---|
| committer | visa <visa@openbsd.org> | 2015-09-26 04:37:18 +0000 |
| commit | 289e3a2f67b10e4278cf18c74ec886149643801e (patch) | |
| tree | 8921606820ed27372734c6a56e5a074b14fe0350 | |
| parent | Let MP-safe interrupt handlers run without the kernel lock on octeon. (diff) | |
| download | wireguard-openbsd-289e3a2f67b10e4278cf18c74ec886149643801e.tar.xz wireguard-openbsd-289e3a2f67b10e4278cf18c74ec886149643801e.zip | |
xheart_splx() has to restore the interrupt mask even on secondary CPUs
because each core has a separate mask. Otherwise the IPI can be left
disabled accidentally on a non-primary CPU when the core uses the
rendezvous mutex:
1. splraise(IPL_IPI) soft-masks the IPI.
2. An IPI hits and the CPU enters the interrupt handler.
3. The handler hard-masks the IPI.
4. The interrupt is not processed because of the CPU's current IPL.
The IPI is left hard-masked on leaving the handler.
5. splx(s) lowers the IPL below IPL_IPI. However, the interrupt's
hardware mask is left unchanged because of the CPU_IS_PRIMARY()
check in xheart_splx().
After this, the system will eventually hang because the CPU does not
respond to IPI requests of other cores.
While here, fix a similar situation with CIU interrupts on octeon.
This might save a few moments of debugging once non-primary CPUs are
allowed to process CIU interrupts.
ok miod@
| -rw-r--r-- | sys/arch/octeon/dev/octeon_intr.c | 4 | ||||
| -rw-r--r-- | sys/arch/sgi/xbow/xheart.c | 6 |
2 files changed, 4 insertions, 6 deletions
diff --git a/sys/arch/octeon/dev/octeon_intr.c b/sys/arch/octeon/dev/octeon_intr.c index fecaa63d45b..2bcb2047b4f 100644 --- a/sys/arch/octeon/dev/octeon_intr.c +++ b/sys/arch/octeon/dev/octeon_intr.c @@ -151,8 +151,8 @@ octeon_splx(int newipl) ci->ci_ipl = newipl; mips_sync(); __asm__ (".set reorder\n"); - if (CPU_IS_PRIMARY(ci)) - octeon_setintrmask(newipl); + octeon_setintrmask(newipl); + /* If we still have softints pending trigger processing. */ if (ci->ci_softpending != 0 && newipl < IPL_SOFTINT) setsoftintr0(); diff --git a/sys/arch/sgi/xbow/xheart.c b/sys/arch/sgi/xbow/xheart.c index b8aa0bf2378..18c4c485736 100644 --- a/sys/arch/sgi/xbow/xheart.c +++ b/sys/arch/sgi/xbow/xheart.c @@ -1,4 +1,4 @@ -/* $OpenBSD: xheart.c,v 1.28 2015/09/08 10:21:50 deraadt Exp $ */ +/* $OpenBSD: xheart.c,v 1.29 2015/09/26 04:37:18 visa Exp $ */ /* * Copyright (c) 2008 Miodrag Vallat. @@ -401,9 +401,7 @@ xheart_splx(int newipl) ci->ci_ipl = newipl; mips_sync(); __asm__ (".set reorder\n"); - - if (CPU_IS_PRIMARY(ci)) - xheart_setintrmask(newipl); + xheart_setintrmask(newipl); /* If we still have softints pending trigger processing. */ if (ci->ci_softpending != 0 && newipl < IPL_SOFTINT) |