diff options
| author |   visa <visa@openbsd.org> | 2017-02-19 09:53:37 +0000 |
|---|---|---|
| committer | visa <visa@openbsd.org> | 2017-02-19 09:53:37 +0000 |
| commit | 7ef12db0e5d4079e0f06c200cbd905ecdc6eab9b (patch) | |
| tree | 016e8728dce7d9cbfaebe97f13fc2339b594feae | |
| parent | Add SMP config and IPI control logic for Loongson 3A. (diff) | |
| download | wireguard-openbsd-7ef12db0e5d4079e0f06c200cbd905ecdc6eab9b.tar.xz wireguard-openbsd-7ef12db0e5d4079e0f06c200cbd905ecdc6eab9b.zip | |
Skip IO interrupt mask update on secondary CPUs when restoring IPL.
The mask is node-wide, and only the primary CPU handles IO interrupts.
| -rw-r--r-- | sys/arch/loongson/loongson/loongson3_intr.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/sys/arch/loongson/loongson/loongson3_intr.c b/sys/arch/loongson/loongson/loongson3_intr.c index fa0f620669c..445c36d4eb0 100644 --- a/sys/arch/loongson/loongson/loongson3_intr.c +++ b/sys/arch/loongson/loongson/loongson3_intr.c @@ -1,4 +1,4 @@ -/* $OpenBSD: loongson3_intr.c,v 1.4 2016/12/12 16:25:47 visa Exp $ */ +/* $OpenBSD: loongson3_intr.c,v 1.5 2017/02/19 09:53:37 visa Exp $ */ /* * Copyright (c) 2016 Visa Hankala @@ -363,8 +363,9 @@ loongson3_splx(int newipl) setipl(ci, newipl); - REGVAL(LS3_IRT_INTENSET(0)) = - loongson3_intem & ~loongson3_imask[newipl]; + if (CPU_IS_PRIMARY(ci)) + REGVAL(LS3_IRT_INTENSET(0)) = + loongson3_intem & ~loongson3_imask[newipl]; if (ci->ci_softpending != 0 && newipl < IPL_SOFTINT) setsoftintr0(); |