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| author |   Jason A. Donenfeld <Jason@zx2c4.com> | 2020-09-07 11:36:54 +0200 |
|---|---|---|
| committer | Jason A. Donenfeld <Jason@zx2c4.com> | 2025-06-10 08:39:08 -0600 |
| commit | 5010f27b9484c1c2fce43fd0f112fa8340a11112 (patch) | |
| tree | 103c751d2391fe666b6bceea335ebcd33ca17a45 | |
| parent | acpi: import acpi_call driver (diff) | |
| download | laptop-kernel-5010f27b9484c1c2fce43fd0f112fa8340a11112.tar.xz laptop-kernel-5010f27b9484c1c2fce43fd0f112fa8340a11112.zip | |
x86/msr: do not warn on writes to OC_MAILBOX
Popular tools, like intel-undervolt, use MSR 0x150 to control the CPU
voltage offset. In fact, evidently the intel_turbo_max_3 driver in-tree
also uses this MSR. So, teach the kernel's MSR list about this, so that
intel-undervolt and other such tools don't spew warnings to dmesg, while
unifying the constant used throughout the kernel.
Fixes: a7e1f67ed29f ("x86/msr: Filter MSR writes")
Cc: Borislav Petkov <bp@suse.de>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
| -rw-r--r-- | arch/x86/include/asm/msr-index.h | 2 | ||||
| -rw-r--r-- | arch/x86/kernel/msr.c | 6 | ||||
| -rw-r--r-- | drivers/platform/x86/intel/turbo_max_3.c | 6 |
3 files changed, 10 insertions, 4 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index e7d2f460fcc6..ed3bb0f8a579 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -240,6 +240,8 @@ #define GDS_MITG_DIS BIT(4) /* Disable GDS mitigation */ #define GDS_MITG_LOCKED BIT(5) /* GDS mitigation locked */ +#define MSR_IA32_OC_MAILBOX 0x00000150 + #define MSR_IA32_SYSENTER_CS 0x00000174 #define MSR_IA32_SYSENTER_ESP 0x00000175 #define MSR_IA32_SYSENTER_EIP 0x00000176 diff --git a/arch/x86/kernel/msr.c b/arch/x86/kernel/msr.c index e17c16c54a37..ba8199c2abf5 100644 --- a/arch/x86/kernel/msr.c +++ b/arch/x86/kernel/msr.c @@ -98,10 +98,14 @@ static int filter_write(u32 reg) if (!__ratelimit(&fw_rs)) return 0; + switch (reg) { + case MSR_IA32_OC_MAILBOX: + return 0; + } + pr_warn("Write to unrecognized MSR 0x%x by %s (pid: %d).\n", reg, current->comm, current->pid); pr_warn("See https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/about for details.\n"); - return 0; } diff --git a/drivers/platform/x86/intel/turbo_max_3.c b/drivers/platform/x86/intel/turbo_max_3.c index 79a0bcdeffb8..2906bcb73f86 100644 --- a/drivers/platform/x86/intel/turbo_max_3.c +++ b/drivers/platform/x86/intel/turbo_max_3.c @@ -17,8 +17,8 @@ #include <asm/cpu_device_id.h> #include <asm/intel-family.h> +#include <asm/msr.h> -#define MSR_OC_MAILBOX 0x150 #define MSR_OC_MAILBOX_CMD_OFFSET 32 #define MSR_OC_MAILBOX_RSP_OFFSET 32 #define MSR_OC_MAILBOX_BUSY_BIT 63 @@ -41,14 +41,14 @@ static int get_oc_core_priority(unsigned int cpu) value = cmd << MSR_OC_MAILBOX_CMD_OFFSET; /* Set the busy bit to indicate OS is trying to issue command */ value |= BIT_ULL(MSR_OC_MAILBOX_BUSY_BIT); - ret = wrmsrl_safe(MSR_OC_MAILBOX, value); + ret = wrmsrl_safe(MSR_IA32_OC_MAILBOX, value); if (ret) { pr_debug("cpu %d OC mailbox write failed\n", cpu); return ret; } for (i = 0; i < OC_MAILBOX_RETRY_COUNT; ++i) { - ret = rdmsrl_safe(MSR_OC_MAILBOX, &value); + ret = rdmsrl_safe(MSR_IA32_OC_MAILBOX, &value); if (ret) { pr_debug("cpu %d OC mailbox read failed\n", cpu); break; |