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authorSheetal <sheetal@nvidia.com>2026-09-21 08:57:02 +0000
committerMark Brown <broonie@kernel.org>2026-09-21 15:24:41 +0200
commit75fc8a3ee5aee72f2fea3b6436170fae175f7f19 (patch)
treee1cc64ec3ee53367f32faf9187a269752a2a04b8
parentASoC: wm8903: Move the DRC QR threshold to the register that holds it (diff)
ASoC: tegra: Fix ASRC Stream6 input threshold control
The Stream6 Input Threshold control points at stream index 4, which is already used by Stream5. The threshold get and put callbacks derive the lane ID from the register offset, so the duplicate index makes Stream6 operate on lane 4 and leaves lane 5 inaccessible from userspace. Use stream index 5 for Stream6. Fixes: a2df8c2d5b36 ("ASoC: tegra: Add Tegra186 based ASRC driver") Signed-off-by: Sheetal <sheetal@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Link: https://patch.msgid.link/20260921085704.1248920-2-sheetal@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r--sound/soc/tegra/tegra186_asrc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/sound/soc/tegra/tegra186_asrc.c b/sound/soc/tegra/tegra186_asrc.c
index 7f360dfaf8b1..d8ae5d997615 100644
--- a/sound/soc/tegra/tegra186_asrc.c
+++ b/sound/soc/tegra/tegra186_asrc.c
@@ -828,7 +828,7 @@ static const struct snd_kcontrol_new tegra186_asrc_controls[] = {
tegra186_asrc_put_input_threshold),
SOC_SINGLE_EXT("Stream6 Input Threshold",
- ASRC_STREAM_REG(TEGRA186_ASRC_RX_THRESHOLD, 4), 0, 3, 0,
+ ASRC_STREAM_REG(TEGRA186_ASRC_RX_THRESHOLD, 5), 0, 3, 0,
tegra186_asrc_get_input_threshold,
tegra186_asrc_put_input_threshold),