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authorSuraj Kandpal <suraj.kandpal@intel.com>2025-11-01 08:54:57 +0530
committerSuraj Kandpal <suraj.kandpal@intel.com>2025-11-01 09:03:56 +0530
commit1dd885d5098db040e5faa5f63b301129e9a04639 (patch)
tree97fcdf2e62c8b4c50ac7de14329d1ad17cc3e3f3 /scripts/Makefile.thinlto
parentdrm/i915/ltphy: Add LT Phy Programming recipe tables (diff)
drm/i915/ltphy: Program the VDR PLL registers for LT PHY
Fetch the tables which need to be used and program it in the specified VDR register space. Everything is done over the respective lanes. Bspec: 68862, 74500 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-10-suraj.kandpal@intel.com
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