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| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-12-23 16:15:38 +0530 |
|---|---|---|
| committer |   Ankit Nautiyal <ankit.k.nautiyal@intel.com> | 2025-12-30 10:02:21 +0530 |
| commit | 192bc98c6fcf8c602ceaf712dc0cd616ebd73f9d (patch) | |
| tree | 57bc6fe7ac1ef517735b37c8a94428ed20803a03 /tools/perf/scripts/python | |
| parent | drm/i915/dsb: Add pipedmc dc balance enable/disable (diff) | |
drm/i915/vrr: Pause DC Balancing for DSB commits
Pause the DMC DC Balancing for the remainder of the
commit so that vmin/vmax won't change after we've baked
them into the DSB vblank evasion commands.
--v2:
- Remove typo. (Ankit)
- Separate vrr enable structuring. (Ankit)
--v3:
- Add gaurd before accessing DC balance bits.
- Remove redundancy checks.
--v4:
- Move events to separate function.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20251223104542.2688548-17-mitulkumar.ajitkumar.golani@intel.com
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions