| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2025-10-15 | EDAC/i10nm: Skip DIMM enumeration on a disabled memory controller |   Qiuxu Zhuo | 1 | -0/+14 |
| 2025-07-15 | EDAC/{skx_common,i10nm}: Use scnprintf() for safer buffer handling |   Wang Haoran | 1 | -9/+9 |
| 2025-07-07 | EDAC/i10nm: Add Intel Granite Rapids-D support | Qiuxu Zhuo | 1 | -1/+11 |
| 2025-04-24 | EDAC/i10nm: Fix the bitwise operation between variables of different sizes | Qiuxu Zhuo | 1 | -2/+2 |
| 2025-04-17 | EDAC/{skx_common,i10nm}: Add RRL support for Intel Granite Rapids server | Qiuxu Zhuo | 1 | -2/+35 |
| 2025-04-17 | EDAC/{skx_common,i10nm}: Refactor show_retry_rd_err_log() | Qiuxu Zhuo | 1 | -89/+69 |
| 2025-04-17 | EDAC/{skx_common,i10nm}: Refactor enable_retry_rd_err_log() | Qiuxu Zhuo | 1 | -98/+133 |
| 2025-04-17 | EDAC/{skx_common,i10nm}: Structure the per-channel RRL registers | Qiuxu Zhuo | 1 | -36/+56 |
| 2025-04-17 | EDAC/i10nm: Explicitly set the modes of the RRL register sets | Qiuxu Zhuo | 1 | -0/+10 |
| 2025-04-17 | EDAC/{skx_common,i10nm}: Fix the loss of saved RRL for HBM pseudo channel 0 | Qiuxu Zhuo | 1 | -16/+19 |
| 2025-02-20 | EDAC/{skx_common,i10nm}: Fix some missing error reports on Emerald Rapids | Qiuxu Zhuo | 1 | -0/+2 |
| 2025-01-21 | Merge tag 'x86_cpu_for_v6.14_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip |   Linus Torvalds | 1 | -11/+12 |
| 2024-12-17 | x86/cpu: Expose only stepping min/max interface |   Dave Hansen | 1 | -10/+11 |
| 2024-12-13 | EDAC/{i10nm,skx,skx_common}: Support UV systems |   Kyle Meyer | 1 | -8/+3 |
| 2024-12-09 | EDAC/i10nm: Add Intel Clearwater Forest server support | Qiuxu Zhuo | 1 | -0/+1 |
| 2024-10-23 | EDAC/{skx_common,i10nm}: Fix incorrect far-memory error source indicator | Qiuxu Zhuo | 1 | -0/+1 |
| 2024-09-03 | EDAC/{skx_common,i10nm}: Remove the AMAP register for determing DDR5 | Qiuxu Zhuo | 1 | -7/+2 |
| 2024-09-03 | EDAC/{skx_common,skx,i10nm}: Move the common debug code to skx_common | Qiuxu Zhuo | 1 | -50/+2 |
| 2024-05-28 | EDAC/i10nm: Switch to new Intel CPU model defines |   Tony Luck | 1 | -10/+10 |
| 2024-02-01 | EDAC/i10nm: Add Intel Grand Ridge micro-server support | Qiuxu Zhuo | 1 | -0/+1 |
| 2023-08-30 | Merge tag 'edac_updates_for_v6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras | Linus Torvalds | 1 | -5/+49 |
| 2023-08-09 | x86/cpu: Fix Crestmont uarch |   Peter Zijlstra | 1 | -1/+1 |
| 2023-07-24 | EDAC/i10nm: Skip the absent memory controllers | Qiuxu Zhuo | 1 | -5/+49 |
| 2023-04-10 | EDAC/i10nm: Add Intel Sierra Forest server support | Qiuxu Zhuo | 1 | -0/+1 |
| 2023-02-08 | EDAC/i10nm: Add driver decoder for Sapphire Rapids server |   Youquan Song | 1 | -33/+69 |
| 2023-01-25 | EDAC/i10nm: Add Intel Granite Rapids server support | Qiuxu Zhuo | 1 | -23/+214 |
| 2023-01-25 | EDAC/i10nm: Make more configurations CPU model specific | Qiuxu Zhuo | 1 | -40/+91 |
| 2023-01-25 | EDAC/i10nm: Add Intel Emerald Rapids server support | Qiuxu Zhuo | 1 | -0/+1 |
| 2022-12-12 | Merge branches 'edac-ghes' and 'edac-misc' into edac-updates-for-v6.2 |   Borislav Petkov (AMD) | 1 | -2/+1 |
| 2022-11-28 | EDAC/i10nm: fix refcount leak in pci_get_dev_wrapper() |   Yang Yingliang | 1 | -2/+1 |
| 2022-10-21 | EDAC: Check for GHES preference in the chipset-specific EDAC drivers |   Jia He | 1 | -0/+3 |
| 2022-09-23 | EDAC/i10nm: Print an extra register set of retry_rd_err_log | Qiuxu Zhuo | 1 | -11/+70 |
| 2022-09-23 | EDAC/i10nm: Retrieve and print retry_rd_err_log registers for HBM | Qiuxu Zhuo | 1 | -17/+67 |
| 2022-09-08 | EDAC/i10nm: Add driver decoder for Ice Lake and Tremont CPUs | Youquan Song | 1 | -2/+132 |
| 2022-01-04 | EDAC/i10nm: Release mdev/mbase when failing to detect HBM | Qiuxu Zhuo | 1 | -0/+9 |
| 2021-08-23 | EDAC/i10nm: Retrieve and print retry_rd_err_log registers | Youquan Song | 1 | -0/+146 |
| 2021-08-23 | EDAC/i10nm: Fix NVDIMM detection | Qiuxu Zhuo | 1 | -3/+3 |
| 2021-06-17 | EDAC/Intel: Do not load EDAC driver when running as a guest | Luck, Tony | 1 | -0/+3 |
| 2021-06-17 | EDAC/i10nm: Add support for high bandwidth memory | Qiuxu Zhuo | 1 | -12/+120 |
| 2021-06-17 | EDAC/i10nm: Add detection of memory levels for ICX/SPR servers | Qiuxu Zhuo | 1 | -0/+39 |
| 2020-11-19 | EDAC/i10nm: Add Intel Sapphire Rapids server support | Qiuxu Zhuo | 1 | -9/+25 |
| 2020-11-19 | EDAC/i10nm: Use readl() to access MMIO registers | Qiuxu Zhuo | 1 | -4/+7 |
| 2020-06-15 | EDAC, {skx,i10nm}: Use CPU stepping macro to pass configurations | Qiuxu Zhuo | 1 | -7/+5 |
| 2020-06-01 | Merge branches 'edac-i10nm' and 'edac-misc' into edac-updates-for-5.8 |   Borislav Petkov | 1 | -5/+24 |
| 2020-05-19 | EDAC/skx: Use the mcmtr register to retrieve close_pg/bank_xor_enable | Qiuxu Zhuo | 1 | -1/+1 |
| 2020-04-27 | EDAC/i10nm: Update driver to support different bus number config register offsets | Qiuxu Zhuo | 1 | -4/+14 |
| 2020-04-27 | EDAC, {skx,i10nm}: Make some configurations CPU model specific | Qiuxu Zhuo | 1 | -4/+13 |
| 2020-03-24 | EDAC: Convert to new X86 CPU match macros |   Thomas Gleixner | 1 | -4/+4 |
| 2019-11-09 | EDAC: Replace EDAC_DIMM_PTR() macro with edac_get_dimm() function |   Robert Richter | 1 | -2/+1 |
| 2019-08-28 | x86/intel: Aggregate microserver naming | Peter Zijlstra | 1 | -2/+2 |
