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path: root/drivers/gpu/drm/xe/xe_ring_ops.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2025-07-17drm/xe: Dont skip TLB invalidations on VFTejas Upadhyay1-12/+10
2025-05-14drm/xe: Save CTX_TIMESTAMP mmio value instead of LRC valueUmesh Nerlige Ramappa1-5/+2
2025-04-07drm/xe: Invalidate L3 read-only cachelines for geometry streams tooKenneth Graunke1-4/+9
2025-03-12drm/xe: Pass flags directly to emit_flush_imm_ggttTvrtko Ursulin1-7/+6
2025-03-12drm/xe: Fix ring flush invalidationTvrtko Ursulin1-9/+6
2025-02-26drm/xe: Add Wa_16021333562 and Wa_14016712196Aradhya Bhatia1-0/+4
2025-02-03drm/xe/pxp: Add VCS inline termination supportDaniele Ceraolo Spurio1-2/+2
2025-01-02Revert "drm/xe: Force write completion of MI_STORE_DATA_IMM"José Roberto de Souza1-4/+2
2024-12-23xe/oa: Fix query mode of operation for OAR/OACUmesh Nerlige Ramappa1-1/+4
2024-12-18drm/xe: Force write completion of MI_STORE_DATA_IMMJosé Roberto de Souza1-2/+4
2024-06-12drm/xe: Emit ctx timestamp copy in ring opsMatthew Brost1-0/+21
2024-06-05drm/xe: flush engine buffers before signalling user fence on all enginesAndrzej Hajda1-2/+16
2024-06-05Revert "drm/xe: flush gtt before signalling user fence on all engines"Andrzej Hajda1-4/+4
2024-05-29drm/xe: Decouple xe_exec_queue and xe_lrcNiranjana Vishwanathapura1-5/+5
2024-05-28drm/xe: flush gtt before signalling user fence on all enginesAndrzej Hajda1-4/+4
2024-05-27drm/xe: Don't initialize fences at xe_sched_job_create()Thomas Hellström1-6/+6
2024-05-27drm/xe: Decouple job seqno and lrc seqnoMatthew Brost1-6/+6
2024-05-09drm/xe: Move xe_gpu_commands.h file to instructions/Michal Wajdeczko1-1/+1
2024-04-08drm/xe/vf: Don't emit access to Global HWSP if VFMichal Wajdeczko1-4/+7
2024-03-28drm/xe: Use ring ops TLB invalidation for rebindsThomas Hellström1-7/+4
2024-02-21drm/xe: Do not include current dir for generated/xe_wa_oob.hDafna Hirschfeld1-1/+2
2024-01-30drm/xe: Use function to emit PIPE_CONTROLJosé Roberto de Souza1-33/+24
2023-12-21drm/xe: Drop some unnecessary header includesMatt Roper1-1/+0
2023-12-21drm/xe/xe2: Add workaround 16020292621Tejas Upadhyay1-0/+20
2023-12-21drm/xe/migrate: fix MI_ARB_ON_OFF usageMatthew Auld1-0/+2
2023-12-21drm/xe: Extract MI_* instructions to their own headerMatt Roper1-1/+2
2023-12-21drm/xe: Clarify number of dwords/qwords stored by MI_STORE_DATA_IMMMatt Roper1-4/+2
2023-12-21drm/xe: Separate number of registers from MI_LRI opcodeMatt Roper1-1/+1
2023-12-21drm/xe: Make MI_FLUSH_DW immediate size more explicitMatt Roper1-5/+5
2023-12-21drm/xe: Use Xe assert macros instead of XE_WARN_ON macroFrancois Dugast1-5/+8
2023-12-21drm/xe: standardize vm-less kernel submissionsDaniele Ceraolo Spurio1-1/+1
2023-12-21drm/xe: fix submissions without vmDaniele Ceraolo Spurio1-4/+4
2023-12-21drm/xe/xe2: AuxCCS is no longer usedMatt Roper1-2/+4
2023-12-21drm/xe: add GSCCS ring opsDaniele Ceraolo Spurio1-5/+21
2023-12-21drm/xe: Rename engine to exec_queueFrancois Dugast1-19/+19
2023-12-21drm/xe: Prefer WARN() over BUG() to avoid crashing the kernelFrancois Dugast1-4/+4
2023-12-19drm/xe: Emit a render cache flush after each rcs/ccs batchThomas Hellström1-0/+35
2023-12-19drm/xe: Invalidate TLB also on bind if in scratch page modeThomas Hellström1-11/+36
2023-12-19drm/xe: Introduce xe_tileMatt Roper1-1/+1
2023-12-19drm/xe: Replace PVC check by engine type checkJosé Roberto de Souza1-3/+3
2023-12-19drm/xe/pvc: Don't try to invalidate AuxCCS TLBMatt Roper1-2/+14
2023-12-19drm/xe: Rename reg field to addrLucas De Marchi1-1/+1
2023-12-19drm/xe/mmio: Use struct xe_regLucas De Marchi1-5/+6
2023-12-19drm/xe: Do not mark 1809175790 as a WALucas De Marchi1-2/+5
2023-12-19drm/xe: Drop gen afixes from registersLucas De Marchi1-4/+4
2023-12-19drm/xe: Reinstate render / compute cache invalidation in ring opsMatthew Brost1-0/+30
2023-12-19drm/xe: Remove dependency on i915_reg.hLucas De Marchi1-3/+1
2023-12-19drm/xe: Remove dependency on intel_gpu_commands.hLucas De Marchi1-24/+25
2023-12-19drm/xe: Remove dependency on intel_lrc_reg.hLucas De Marchi1-1/+1
2023-12-19drm/xe: Remove dependency on intel_gt_regs.hLucas De Marchi1-1/+1
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