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2025-10-23phy: cadence: cdns-dphy: Update calibration wait time for startup state machineDevarsh Thakkar1-1/+3
[ Upstream commit 2c27aaee934a1b5229152fe33a14f1fdf50da143 ] Do read-modify-write so that we re-use the characterized reset value as specified in TRM [1] to program calibration wait time which defines number of cycles to wait for after startup state machine is in bandgap enable state. This fixes PLL lock timeout error faced while using RPi DSI Panel on TI's AM62L and J721E SoC since earlier calibration wait time was getting overwritten to zero value thus failing the PLL to lockup and causing timeout. [1] AM62P TRM (Section 14.8.6.3.2.1.1 DPHY_TX_DPHYTX_CMN0_CMN_DIG_TBIT2): Link: https://www.ti.com/lit/pdf/spruj83 Cc: stable@vger.kernel.org Fixes: 7a343c8bf4b5 ("phy: Add Cadence D-PHY support") Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Tested-by: Harikrishna Shenoy <h-shenoy@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Link: https://lore.kernel.org/r/20250704125915.1224738-3-devarsht@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-10-23phy: cadence: cdns-dphy: Fix PLL lock and O_CMN_READY pollingDevarsh Thakkar1-32/+92
[ Upstream commit 284fb19a3ffb1083c3ad9c00d29749d09dddb99c ] PLL lockup and O_CMN_READY assertion can only happen after common state machine gets enabled by programming DPHY_CMN_SSM register, but driver was polling them before the common state machine was enabled which is incorrect. This is as per the DPHY initialization sequence as mentioned in J721E TRM [1] at section "12.7.2.4.1.2.1 Start-up Sequence Timing Diagram". It shows O_CMN_READY polling at the end after common configuration pin setup where the common configuration pin setup step enables state machine as referenced in "Table 12-1533. Common Configuration-Related Setup mentions state machine" To fix this : - Add new function callbacks for polling on PLL lock and O_CMN_READY assertion. - As state machine and clocks get enabled in power_on callback only, move the clock related programming part from configure callback to power_on callback and poll for the PLL lockup and O_CMN_READY assertion after state machine gets enabled. - The configure callback only saves the PLL configuration received from the client driver which will be applied later on in power_on callback. - Add checks to ensure configure is called before power_on and state machine is in disabled state before power_on callback is called. - Disable state machine in power_off so that client driver can re-configure the PLL by following up a power_off, configure, power_on sequence. [1]: https://www.ti.com/lit/zip/spruil1 Cc: stable@vger.kernel.org Fixes: 7a343c8bf4b5 ("phy: Add Cadence D-PHY support") Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Tested-by: Harikrishna Shenoy <h-shenoy@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Link: https://lore.kernel.org/r/20250704125915.1224738-2-devarsht@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-10-23phy: cdns-dphy: Store hs_clk_rate and return itTomi Valkeinen1-0/+5
[ Upstream commit 689a54acb56858c85de8c7285db82b8ae6dbf683 ] The DPHY driver does not return the actual hs_clk_rate, so the DSI driver has no idea what clock was actually achieved. Set the realized hs_clk_rate to the opts struct, so that the DSI driver gets it back. Reviewed-by: Aradhya Bhatia <aradhya.bhatia@linux.dev> Tested-by: Parth Pancholi <parth.pancholi@toradex.com> Tested-by: Jayesh Choudhary <j-choudhary@ti.com> Acked-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Link: https://lore.kernel.org/r/20250723-cdns-dphy-hs-clk-rate-fix-v1-1-d4539d44cbe7@ideasonboard.com Signed-off-by: Vinod Koul <vkoul@kernel.org> Stable-dep-of: 284fb19a3ffb ("phy: cadence: cdns-dphy: Fix PLL lock and O_CMN_READY polling") Signed-off-by: Sasha Levin <sashal@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2025-10-15phy: rockchip: naneng-combphy: Enable U3 OTG port for RK3568Jonas Karlman1-0/+12
[ Upstream commit 7bb14b61b7d03db770b7e8871493f5b9b2be2b79 ] The boot firmware may disable the U3 port early during boot and leave it up to the controller or PHY driver to re-enable U3 when needed. The Rockchip USBDP PHY driver currently does this for RK3576 and RK3588, something the Rockchip Naneng Combo PHY driver never does for RK3568. This may result in USB 3.0 ports being limited to only using USB 2.0 or in special cases not working at all on RK3568. Write to PIPE_GRF USB3OTGx_CON1 reg to ensure the U3 port is enabled when a PHY with PHY_TYPE_USB3 mode is used. Fixes: 7160820d742a ("phy: rockchip: add naneng combo phy for RK3568") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250723072324.2246498-1-jonas@kwiboo.se Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2025-09-01phy: qcom: qmp-pcie: Fix PHY initialization when powered down by firmwareStephan Gerhold1-6/+19
Commit 0cc22f5a861c ("phy: qcom: qmp-pcie: Add PHY register retention support") added support for using the "no_csr" reset to skip configuration of the PHY if the init sequence was already applied by the boot firmware. The expectation is that the PHY is only turned on/off by using the "no_csr" reset, instead of powering it down and re-programming it after a full reset. The boot firmware on X1E does not fully conform to this expectation: If the PCIe3 link fails to come up (e.g. because no PCIe card is inserted), the firmware powers down the PHY using the QPHY_PCS_POWER_DOWN_CONTROL register. The QPHY_START_CTRL register is kept as-is, so the driver assumes the PHY is already initialized and skips the configuration/power up sequence. The PHY won't come up again without clearing the QPHY_PCS_POWER_DOWN_CONTROL, so eventually initialization fails: qcom-qmp-pcie-phy 1be0000.phy: phy initialization timed-out phy phy-1be0000.phy.0: phy poweron failed --> -110 qcom-pcie 1bd0000.pcie: cannot initialize host qcom-pcie 1bd0000.pcie: probe with driver qcom-pcie failed with error -110 This can be reliably reproduced on the X1E CRD, QCP and Devkit when no card is inserted for PCIe3. Fix this by checking the QPHY_PCS_POWER_DOWN_CONTROL register in addition to QPHY_START_CTRL. If the PHY is powered down with the register, it doesn't conform to the expectations for using the "no_csr" reset, so we fully re-initialize with the normal reset sequence. Also check the register more carefully to ensure all of the bits we expect are actually set. A simple !!(readl()) is not enough, because the PHY might be only partially set up with some of the expected bits set. Cc: stable@vger.kernel.org Fixes: 0cc22f5a861c ("phy: qcom: qmp-pcie: Add PHY register retention support") Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250821-phy-qcom-qmp-pcie-nocsr-fix-v3-1-4898db0cc07c@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-09-01phy: ti: gmii-sel: Always write the RGMII ID settingMichael Walle1-8/+39
Some SoCs are just validated with the TX delay enabled. With commit ca13b249f291 ("net: ethernet: ti: am65-cpsw: fixup PHY mode for fixed RGMII TX delay"), the network driver will patch the delay setting on the fly assuming that the TX delay setting is fixed. In reality, the TX delay is configurable and just skipped in the documentation. There are bootloaders, which will disable the TX delay and this will lead to a transmit path which doesn't add any delays at all. Fix that by always writing the RGMII_ID setting and report an error for unsupported RGMII delay modes. This is safe to do and shouldn't break any boards in mainline because the fixed delay is only introduced for gmii-sel compatibles which are used together with the am65-cpsw-nuss driver and also contains the commit above. Fixes: ca13b249f291 ("net: ethernet: ti: am65-cpsw: fixup PHY mode for fixed RGMII TX delay") Signed-off-by: Michael Walle <mwalle@kernel.org> Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Link: https://lore.kernel.org/r/20250819065622.1019537-1-mwalle@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-08-12phy: ti-pipe3: fix device leak at unbindJohan Hovold1-0/+13
Make sure to drop the reference to the control device taken by of_find_device_by_node() during probe when the driver is unbound. Fixes: 918ee0d21ba4 ("usb: phy: omap-usb3: Don't use omap_get_control_dev()") Cc: stable@vger.kernel.org # 3.13 Cc: Roger Quadros <rogerq@kernel.org> Signed-off-by: Johan Hovold <johan@kernel.org> Link: https://lore.kernel.org/r/20250724131206.2211-4-johan@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-08-12phy: ti: omap-usb2: fix device leak at unbindJohan Hovold1-0/+13
Make sure to drop the reference to the control device taken by of_find_device_by_node() during probe when the driver is unbound. Fixes: 478b6c7436c2 ("usb: phy: omap-usb2: Don't use omap_get_control_dev()") Cc: stable@vger.kernel.org # 3.13 Cc: Roger Quadros <rogerq@kernel.org> Signed-off-by: Johan Hovold <johan@kernel.org> Link: https://lore.kernel.org/r/20250724131206.2211-3-johan@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-08-12phy: tegra: xusb: fix device and OF node leak at probeJohan Hovold1-1/+5
Make sure to drop the references taken to the PMC OF node and device by of_parse_phandle() and of_find_device_by_node() during probe. Note the holding a reference to the PMC device does not prevent the PMC regmap from going away (e.g. if the PMC driver is unbound) so there is no need to keep the reference. Fixes: 2d1021487273 ("phy: tegra: xusb: Add wake/sleepwalk for Tegra210") Cc: stable@vger.kernel.org # 5.14 Cc: JC Kuo <jckuo@nvidia.com> Signed-off-by: Johan Hovold <johan@kernel.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250724131206.2211-2-johan@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-08-12phy: qualcomm: phy-qcom-eusb2-repeater: fix override propertiesPengyu Luo1-2/+2
property "qcom,tune-usb2-preem" is for EUSB2_TUNE_USB2_PREEM property "qcom,tune-usb2-amplitude" is for EUSB2_TUNE_IUSB2 The downstream correspondence is as follows: EUSB2_TUNE_USB2_PREEM: Tx pre-emphasis tuning EUSB2_TUNE_IUSB2: HS trasmit amplitude EUSB2_TUNE_SQUELCH_U: Squelch detection threshold EUSB2_TUNE_HSDISC: HS disconnect threshold EUSB2_TUNE_EUSB_SLEW: slew rate Fixes: 31bc94de7602 ("phy: qualcomm: phy-qcom-eusb2-repeater: Don't zero-out registers") Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20250812093957.32235-1-mitltlatltl@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-08-01Merge tag 'phy-for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phyLinus Torvalds32-287/+1535
Pull phy updates from Vinod Koul: "New Support: - Qualcomm Milos Synopsys eUSB2 PHY, SM8750 QMP phy support, M31 eUSB2 PHY driver - Samsung Exynos990 usbdrd phy, Exynos7870 MIPI phy support - Renesas RZ/V2N usb2-phy support Updates: - Bulk Yaml binding conversion By Rob H (too many to be listed) - cadence: Sierra PCIe, USB PHY multilink configuration support - Qualcomm refactoring of UFS PHY reset and UFS driver support for phy calibrate API" * tag 'phy-for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (74 commits) phy: qcom: phy-qcom-m31: Update IPQ5332 M31 USB phy initialization sequence dt-bindings: phy: Convert brcm,sr-usb-combo-phy to DT schema dt-bindings: phy: Convert ti,da830-usb-phy to DT schema dt-bindings: phy: marvell,mmp2-usb-phy: Drop status from the example dt-bindings: phy: mixel, mipi-dsi-phy: Allow assigned-clock* properties phy: exynos-mipi-video: correct cam0 sysreg property name for exynos7870 phy: qcom: phy-qcom-snps-eusb2: Update init sequence per HPG 1.0.2 phy: qcom: phy-qcom-snps-eusb2: Add missing write from init sequence dt-bindings: phy: qcom,snps-eusb2: document the Milos Synopsys eUSB2 PHY dt-bindings: usb: qcom,snps-dwc3: Add Milos compatible phy: rockchip-pcie: Properly disable TEST_WRITE strobe signal phy: rockchip-pcie: Enable all four lanes if required dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings for QCS615 phy: qcom: qmp-combo: Add missing PLL (VCO) configuration on SM8750 phy: qcom: m31-eusb2: drop registration printk phy: qcom: m31-eusb2: fix match data santity check phy: qcom: qmp-pcie: Update PHY settings for QCS8300 & SA8775P phy: qualcomm: phy-qcom-eusb2-repeater: Don't zero-out registers dt-bindings: phy: qcom,snps-eusb2-repeater: Remove default tuning values phy: mediatek: tphy: Cleanup and document slew calibration ...
2025-07-31Merge tag 'for-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supplyLinus Torvalds1-1/+1
Pull power supply and reset updates from Sebastian Reichel: "Power-supply core: - battery-info: replace any DT specific bits with fwnode usage - replace any device-tree code with generic fwnode based handling Power-supply drivers: - ug3105_battery: use battery-info API - qcom_battmgr: report capacity - qcom_battmgr: support LiPo battery reporting - add missing missing power-supply ref to a bunch of DT bindings - update drivers regarding pm_runtime_autosuspend() usage - misc minor fixes and cleanups Reset drivers: - misc minor cleanups" * tag 'for-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply: (32 commits) power: supply: core: fix static checker warning power: supply: twl4030_charger: Remove redundant pm_runtime_mark_last_busy() calls power: supply: bq24190: Remove redundant pm_runtime_mark_last_busy() calls MAINTAINERS: rectify file entry in QUALCOMM SMB CHARGER DRIVER power: supply: max1720x correct capacity computation MAINTAINERS: add myself as smbx charger driver maintainer power: supply: pmi8998_charger: rename to qcom_smbx power: supply: qcom_pmi8998_charger: fix wakeirq power: supply: max14577: Handle NULL pdata when CONFIG_OF is not set power: return the correct error code power: reset: POWER_RESET_TORADEX_EC should depend on ARCH_MXC power: supply: cpcap-charger: Fix null check for power_supply_get_by_name power: supply: bq25980_charger: Constify reg_default array power: supply: bq256xx_charger: Constify reg_default array power: reset: at91-sama5d2_shdwc: Refactor wake-up source logging to use dev_info power: reset: qcom-pon: Rename variables to use generic naming power: supply: qcom_battmgr: Add lithium-polymer entry power: supply: qcom_battmgr: Report battery capacity power: supply: bq24190: Free battery_info power: supply: ug3105_battery: Switch to power_supply_batinfo_ocv2cap() ...
2025-07-22phy: qcom: phy-qcom-m31: Update IPQ5332 M31 USB phy initialization sequenceKathiravan Thirumoorthy1-4/+10
The current configuration used for the IPQ5332 M31 USB PHY fails the Near End High Speed Signal Quality compliance test. To resolve this, update the initialization sequence as specified in the Hardware Design Document. Fixes: 08e49af50701 ("phy: qcom: Introduce M31 USB PHY driver") Cc: stable@kernel.org Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250630-ipq5332_hsphy_complaince-v2-1-63621439ebdb@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-07-22phy: exynos-mipi-video: correct cam0 sysreg property name for exynos7870Kaustabh Chakraborty1-1/+1
Fix the cam0 sysreg property name (samsung,cam0-sysreg), which has been erroneously declared as samsung,cam-sysreg. This follows the same name used in Exynos5433 PHY. Fixes: 543f5e314282 ("phy: exynos-mipi-video: introduce support for exynos7870") Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Link: https://lore.kernel.org/r/20250710-exynos7870-mipi-phy-fix-v2-1-5cf50d69c9d7@disroot.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-07-22phy: qcom: phy-qcom-snps-eusb2: Update init sequence per HPG 1.0.2Luca Weiss1-1/+1
The eUSB2 HPG version 1.0.2 asks to clear bits [7:1] on all targets. Implement that change in the driver to follow. See also https://lore.kernel.org/linux-arm-msm/7d073433-f254-4d75-a68b-d184f900294a@oss.qualcomm.com/ Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250715-sm7635-eusb-phy-v3-4-6c3224085eb6@fairphone.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-07-22phy: qcom: phy-qcom-snps-eusb2: Add missing write from init sequenceLuca Weiss1-0/+3
As per a commit from Qualcomm's downstream 6.1 kernel[0], the init sequence is missing setting the CMN_CTRL_OVERRIDE_EN bit back to 0 at the end, as per the 'latest' HPG revision (as of November 2023). [0] https://git.codelinaro.org/clo/la/kernel/qcom/-/commit/b77774a89e3fda3246e09dd39e16e2ab43cd1329 Fixes: 80090810f5d3 ("phy: qcom: Add QCOM SNPS eUSB2 driver") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20250715-sm7635-eusb-phy-v3-3-6c3224085eb6@fairphone.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-07-22phy: rockchip-pcie: Properly disable TEST_WRITE strobe signalGeraldo Nascimento1-2/+1
pcie_conf is used to touch TEST_WRITE strobe signal. This signal should be enabled, a little time waited, and then disabled. Current code clearly was copy-pasted and never disables the strobe signal. Adjust the define. While at it, remove PHY_CFG_RD_MASK which has been unused since 64cdc0360811 ("phy: rockchip-pcie: remove unused phy_rd_cfg function"). Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Geraldo Nascimento <geraldogabriel@gmail.com> Link: https://lore.kernel.org/r/d514d5d5627680caafa8b7548cbdfee4307f5440.1751322015.git.geraldogabriel@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-07-22phy: rockchip-pcie: Enable all four lanes if requiredValmantas Paliksa1-6/+6
Current code enables only Lane 0 because pwr_cnt will be incremented on first call to the function. Let's reorder the enablement code to enable all 4 lanes through GRF. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Valmantas Paliksa <walmis@gmail.com> Signed-off-by: Geraldo Nascimento <geraldogabriel@gmail.com> Reviewed-by: Robin Murphy <robin.murphy@arm.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/16b610aab34e069fd31d9f57260c10df2a968f80.1751322015.git.geraldogabriel@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-07-15phy: qcom: fix error code in snps_eusb2_hsphy_probe()Harshit Mogalapalli1-2/+4
When phy->ref_clk is NULL PTR_ERR(NULL) will be a success. Fix this by using -ENOENT when phy->ref_clk is NULL instead. Fixes: 80090810f5d3 ("phy: qcom: Add QCOM SNPS eUSB2 driver") Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Closes: https://lore.kernel.org/all/aDCbeuCTy9zyWJAM@stanley.mountain/ Signed-off-by: Harshit Mogalapalli <harshit.m.mogalapalli@oracle.com> Link: https://lore.kernel.org/r/20250710172403.2593193-1-harshit.m.mogalapalli@oracle.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-26phy: qcom: qmp-combo: Add missing PLL (VCO) configuration on SM8750Krzysztof Kozlowski1-0/+3
Add missing DP PHY status and VCO clock configuration registers to fix configuring the VCO rate on SM8750. Without proper VCO rate setting, it works on after-reset half of rate which is not enough for DP over USB to work as seen on logs: [drm:msm_dp_ctrl_link_train_1_2] *ERROR* max v_level reached [drm:msm_dp_ctrl_link_train_1_2] *ERROR* link training #1 on phy 0 failed. ret=-11 Fixes: c4364048baf4 ("phy: qcom: qmp-combo: Add new PHY sequences for SM8750") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250616062541.7167-2-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-26phy: qcom: m31-eusb2: drop registration printkJohan Hovold1-2/+0
Drivers should generally be quiet on successful probe so drop the registration printk from the recently added M31 EUSB2 driver. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250617080401.11147-1-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-26phy: qcom: m31-eusb2: fix match data santity checkJohan Hovold1-1/+1
The device_get_match_data() helper returns NULL if a new entry is ever added without corresponding match data. Fixes: 9c8504861cc4 ("phy: qcom: Add M31 based eUSB2 PHY driver") Cc: Wesley Cheng <quic_wcheng@quicinc.com> Cc: Melody Olvera <melody.olvera@oss.qualcomm.com> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250617080503.11262-1-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-26phy: qcom: qmp-pcie: Update PHY settings for QCS8300 & SA8775PMrinmay Sarkar5-41/+66
Update the PHY settings to align with the latest PCIe PHY Hardware Programming Guide for both PCIe controllers on the SA8775P platform. Add the ln_shrd region for SA8775P, incorporating new register writes as specified in the updated Hardware Programming Guide. Update pcs table for QCS8300, since both QCS8300 and SA8775P are closely related and share same pcs settings. Signed-off-by: Mrinmay Sarkar <mrinmay.sarkar@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250617-update_phy-v5-1-2df83ed6a373@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-26phy: qualcomm: phy-qcom-eusb2-repeater: Don't zero-out registersLuca Weiss1-55/+32
Zeroing out registers does not happen in the downstream kernel, and will "tune" the repeater in surely unexpected ways since most registers don't have a reset value of 0x0. Stop doing that and instead just set the registers that are in the init sequence (though long term I don't think there's actually PMIC-specific init sequences, there's board specific tuning, but that's a story for another day). Fixes: 99a517a582fc ("phy: qualcomm: phy-qcom-eusb2-repeater: Zero out untouched tuning regs") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20250617-eusb2-repeater-tuning-v2-2-ed6c484f18ee@fairphone.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-26phy: mediatek: tphy: Cleanup and document slew calibrationAngeloGioacchino Del Regno1-18/+27
While it's true that, generally, the T-PHY V3 does not support the slew calibration process, some minor versions of it actually do, moreover, some SoCs may not support this even though the version of the PHY IP does. The reference clock and rate coefficient parameters are used only for slew calibration: move those to platform data, then document and change the checks in hs_slew_rate_calibrate() to perform the calibration only if: - EYE value was not supplied (pre-calculated calibration); and - Slew reference clock value is present (not zero); and - Slew coefficient is present (not zero). Moreover, change the probe function to always check if both the slew reference clock and coefficient properties are present and, if not, assign the value from platform data (which, as reminder, if not added means that it's zero!), instead of checking the PHY IP version. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250623120315.109881-3-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-26phy: mediatek: tphy: Clarify and add kerneldoc to mtk_phy_pdataAngeloGioacchino Del Regno1-10/+10
As struct mtk_phy_pdata was almost fully documented, transfer the comments into kerneldoc on top. While at it, also rewrite the comments to both improve the writing writing and the actual information in the documentation, and add a description for the `version` member of the structure. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250623120315.109881-2-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-22power: supply: core: rename power_supply_get_by_phandle to power_supply_get_by_referenceSebastian Reichel1-1/+1
(devm_)power_supply_get_by_phandle now internally uses fwnode and are no longer DT specific. Thus drop the ifdef check for CONFIG_OF and rename to (devm_)power_supply_get_by_reference to avoid the DT terminology. Reviewed-by: Hans de Goede <hansg@kernel.org> Link: https://lore.kernel.org/r/20250430-psy-core-convert-to-fwnode-v2-5-f9643b958677@collabora.com Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
2025-06-17phy: qcom: add linux/bitfield.h header to fix a build errorRandy Dunlap1-0/+1
Add the <linux/bitfield.h> header to prevent a build error: drivers/phy/qualcomm/phy-qcom-m31-eusb2.c: In function 'm31eusb2_phy_init': drivers/phy/qualcomm/phy-qcom-m31-eusb2.c:210:37: error: implicit declaration of function 'FIELD_PREP' [-Wimplicit-function-declaration] 210 | FIELD_PREP(FSEL, data->fsel)); Fixes: 9c8504861cc4 ("phy: qcom: Add M31 based eUSB2 PHY driver") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Wesley Cheng <quic_wcheng@quicinc.com> Cc: Melody Olvera <melody.olvera@oss.qualcomm.com> Cc: Vinod Koul <vkoul@kernel.org> Cc: Kishon Vijay Abraham I <kishon@kernel.org> Cc: linux-phy@lists.infradead.org Cc: linux-arm-msm@vger.kernel.org Link: https://lore.kernel.org/r/20250617034249.2067135-1-rdunlap@infradead.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-16phy: drop probe registration printksJohan Hovold12-21/+4
Drivers should generally be quiet on successful probe, but this is not followed by some PHY drivers, for example: snps-eusb2-hsphy 88e1000.phy: Registered Snps-eUSB2 phy qcom-eusb2-repeater c432000.spmi:pmic@7:phy@fd00: Registered Qcom-eUSB2 repeater qcom-eusb2-repeater c432000.spmi:pmic@a:phy@fd00: Registered Qcom-eUSB2 repeater qcom-eusb2-repeater c432000.spmi:pmic@b:phy@fd00: Registered Qcom-eUSB2 repeater snps-eusb2-hsphy fd3000.phy: Registered Snps-eUSB2 phy snps-eusb2-hsphy fd9000.phy: Registered Snps-eUSB2 phy snps-eusb2-hsphy fde000.phy: Registered Snps-eUSB2 phy snps-eusb2-hsphy 88e0000.phy: Registered Snps-eUSB2 phy snps-eusb2-hsphy 88e2000.phy: Registered Snps-eUSB2 phy Drop (or demote to debug level) unnecessary registration info messages to make boot logs a little less noisy. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20250523085112.11287-1-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-16phy: cadence-torrent: Add PCIe multilink + USB with same SSC register config for 100 MHz refclkSwapnil Jakhade1-8/+150
Add register sequences and support for PCIe multilink + USB configuration for 100MHz reference clock. The same SSC is used for both PCIe and USB. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Co-developed-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20250616064705.3225758-3-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-16phy: cadence-torrent: Add PCIe multilink configuration for 100 MHz refclkSwapnil Jakhade1-1/+129
Add register sequences to support PCIe multilink configuration for 100MHz reference clock. Maximum two PCIe links are supported. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20250616064705.3225758-2-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15phy: phy-snps-eusb2: clean up id table sentinelJohan Hovold1-1/+3
Use a more common format for the id table sentinel for consistency and symmetry. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20250523084839.11015-8-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15phy: phy-snps-eusb2: drop unnecessary loop index declarationsJohan Hovold1-2/+2
There is already a loop index variable declared at function scope so drop the unnecessary overloaded loop declarations. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20250523084839.11015-7-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15phy: phy-snps-eusb2: fix optional phy lookup parameterJohan Hovold1-1/+1
The devm_of_phy_optional_get() takes an optional name argument as its third parameter and not an index like the recently replaced devm_of_phy_get_by_index(). Replace 0 with an explicit NULL for consistency and readability. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20250523084839.11015-6-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15phy: phy-snps-eusb2: clean up error messagesJohan Hovold1-7/+7
Clean up the error messages by using a consistent format with a colon followed by a space and an errno (or unsupported frequency). Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20250523084839.11015-5-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15phy: phy-snps-eusb2: rename phy_init() clock error labelJohan Hovold1-4/+4
Rename the clock error label which is now used to disable all clocks and not just the ref clock on phy_init() errors. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20250523084839.11015-4-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15phy: phy-snps-eusb2: fix repeater imbalance on phy_init() failureJohan Hovold1-2/+3
Make sure to disable the repeater PHY also on phy_init() failure. Fixes: 3584f6392f09 ("phy: qcom: phy-qcom-snps-eusb2: Add support for eUSB2 repeater") Cc: Abel Vesa <abel.vesa@linaro.org> Cc: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20250523084839.11015-3-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15phy: phy-snps-eusb2: fix clock imbalance on phy_exit()Johan Hovold1-1/+1
Make sure to disable all clocks enabled at phy_init() also on phy_exit(). Fixes: c4098f3e6134 ("phy: phy-snps-eusb2: add support for exynos2200") Cc: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20250523084839.11015-2-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15phy: qcom: Add M31 based eUSB2 PHY driverWesley Cheng3-0/+336
SM8750 utilizes an eUSB2 PHY from M31. Add the initialization sequences to bring it out of reset and into an operational state. This differs to the M31 USB driver, in that the M31 eUSB2 driver will require a connection to an eUSB2 repeater. This PHY driver will handle the initialization of the associated eUSB2 repeater when required. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com> Signed-off-by: Melody Olvera <melody.olvera@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250527-sm8750_usb_master-v6-6-d58de3b41d34@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15phy: qcom: Update description for QCOM based eUSB2 repeaterWesley Cheng1-3/+3
The eUSB2 repeater that exists in the QCOM PMICs are utilized for several different eUSB2 PHY vendors, such as M31 or Synopsys. Hence, the wording needs to be updated to remove associations to a specific vendor. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com> Signed-off-by: Melody Olvera <melody.olvera@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250527-sm8750_usb_master-v6-5-d58de3b41d34@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15phy: qcom: qmp-combo: Add new PHY sequences for SM8750Wesley Cheng6-0/+428
Add new register offsets and PHY values for SM8750. Some of the previous definitions can be leveraged from older PHY versions as offsets within registers have not changed. This also adds the required PHY sequence that is recommended after running hardware characterization. Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com> Signed-off-by: Melody Olvera <melody.olvera@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250527-sm8750_usb_master-v6-4-d58de3b41d34@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15phy: use per-PHY lockdep keysDmitry Baryshkov1-1/+4
If the PHY driver uses another PHY internally (e.g. in case of eUSB2, repeaters are represented as PHYs), then it would trigger the following lockdep splat because all PHYs use a single static lockdep key and thus lockdep can not identify whether there is a dependency or not and reports a false positive. Make PHY subsystem use dynamic lockdep keys, assigning each driver a separate key. This way lockdep can correctly identify dependency graph between mutexes. ============================================ WARNING: possible recursive locking detected 6.15.0-rc7-next-20250522-12896-g3932f283970c #3455 Not tainted -------------------------------------------- kworker/u51:0/78 is trying to acquire lock: ffff0008116554f0 (&phy->mutex){+.+.}-{4:4}, at: phy_init+0x4c/0x12c but task is already holding lock: ffff000813c10cf0 (&phy->mutex){+.+.}-{4:4}, at: phy_init+0x4c/0x12c other info that might help us debug this: Possible unsafe locking scenario: CPU0 ---- lock(&phy->mutex); lock(&phy->mutex); *** DEADLOCK *** May be due to missing lock nesting notation 4 locks held by kworker/u51:0/78: #0: ffff000800010948 ((wq_completion)events_unbound){+.+.}-{0:0}, at: process_one_work+0x18c/0x5ec #1: ffff80008036bdb0 (deferred_probe_work){+.+.}-{0:0}, at: process_one_work+0x1b4/0x5ec #2: ffff0008094ac8f8 (&dev->mutex){....}-{4:4}, at: __device_attach+0x38/0x188 #3: ffff000813c10cf0 (&phy->mutex){+.+.}-{4:4}, at: phy_init+0x4c/0x12c stack backtrace: CPU: 0 UID: 0 PID: 78 Comm: kworker/u51:0 Not tainted 6.15.0-rc7-next-20250522-12896-g3932f283970c #3455 PREEMPT Hardware name: Qualcomm CRD, BIOS 6.0.240904.BOOT.MXF.2.4-00528.1-HAMOA-1 09/ 4/2024 Workqueue: events_unbound deferred_probe_work_func Call trace: show_stack+0x18/0x24 (C) dump_stack_lvl+0x90/0xd0 dump_stack+0x18/0x24 print_deadlock_bug+0x258/0x348 __lock_acquire+0x10fc/0x1f84 lock_acquire+0x1c8/0x338 __mutex_lock+0xb8/0x59c mutex_lock_nested+0x24/0x30 phy_init+0x4c/0x12c snps_eusb2_hsphy_init+0x54/0x1a0 phy_init+0xe0/0x12c dwc3_core_init+0x450/0x10b4 dwc3_core_probe+0xce4/0x15fc dwc3_probe+0x64/0xb0 platform_probe+0x68/0xc4 really_probe+0xbc/0x298 __driver_probe_device+0x78/0x12c driver_probe_device+0x3c/0x160 __device_attach_driver+0xb8/0x138 bus_for_each_drv+0x84/0xe0 __device_attach+0x9c/0x188 device_initial_probe+0x14/0x20 bus_probe_device+0xac/0xb0 deferred_probe_work_func+0x8c/0xc8 process_one_work+0x208/0x5ec worker_thread+0x1c0/0x368 kthread+0x14c/0x20c ret_from_fork+0x10/0x20 Fixes: 3584f6392f09 ("phy: qcom: phy-qcom-snps-eusb2: Add support for eUSB2 repeater") Fixes: e2463559ff1d ("phy: amlogic: Add Amlogic AXG PCIE PHY Driver") Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Reported-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/lkml/ZnpoAVGJMG4Zu-Jw@hovoldconsulting.com/ Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250605-phy-subinit-v3-1-1e1e849e10cd@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15phy: qcom-qmp-ufs: refactor qmp_ufs_power_offNitin Rawat1-7/+0
In qmp_ufs_power_off, the PHY is already powered down by asserting QPHY_PCS_POWER_DOWN_CONTROL. Therefore, additional phy_reset and stopping SerDes are unnecessary. Also this approach does not align with the phy HW programming guide. Thus, refactor qmp_ufs_power_off to remove the phy_reset and stop SerDes calls to simplify the code and ensure alignment with the PHY HW programming guide. Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20250526153821.7918-10-quic_nitirawa@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15phy: qcom-qmp-ufs: Remove qmp_ufs_exit() and Inline qmp_ufs_com_exit()Nitin Rawat1-14/+3
qmp_ufs_exit() is a wrapper function. It only calls qmp_ufs_com_exit(). Remove it to simplify the ufs phy driver. Additonally partial Inline(dropping the reset assert) qmp_ufs_com_exit into qmp_ufs_power_off function to avoid unnecessary function call and to align with the Phy programming guide. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> Link: https://lore.kernel.org/r/20250526153821.7918-9-quic_nitirawa@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15phy: qcom-qmp-ufs: Rename qmp_ufs_power_offNitin Rawat1-18/+1
Rename qmp_ufs_disable to qmp_ufs_power_off to better represent its functionality. Additionally, inline qmp_ufs_exit into qmp_ufs_power_off function to preserve the functionality of .power_off. There is no functional change. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> Link: https://lore.kernel.org/r/20250526153821.7918-8-quic_nitirawa@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15phy: qcom-qmp-ufs: Remove qmp_ufs_com_init()Nitin Rawat1-26/+15
The qmp_ufs_power_on() function acts as a wrapper, solely invoking qmp_ufs_com_init(). Additionally, the code within qmp_ufs_com_init() does not correspond well with its name. Therefore, to enhance the readability and eliminate unnecessary function call inline qmp_ufs_com_init() into qmp_ufs_power_on(). There is no change to the functionality. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> Link: https://lore.kernel.org/r/20250526153821.7918-7-quic_nitirawa@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15phy: qcom-qmp-ufs: Refactor UFS PHY resetNitin Rawat1-28/+31
Refactor the UFS PHY reset handling to parse the reset logic only once during initialization, instead of every resume. As part of this change, move the UFS PHY reset parsing logic from qmp_phy_power_on to the new qmp_ufs_phy_init function introduced as part of phy_ops::init callback. Co-developed-by: Ram Kumar Dwivedi <quic_rdwivedi@quicinc.com> Signed-off-by: Ram Kumar Dwivedi <quic_rdwivedi@quicinc.com> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250526153821.7918-6-quic_nitirawa@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15phy: qcom-qmp-ufs: Refactor phy_power_on and phy_calibrate callbacksNitin Rawat1-20/+6
Commit 052553af6a31 ("ufs/phy: qcom: Refactor to use phy_init call") puts enabling regulators & clks, calibrating UFS PHY, starting serdes and polling PCS ready status into phy_power_on. In Current code regulators enable, clks enable, calibrating UFS PHY, start_serdes and polling PCS_ready_status are part of phy_power_on. UFS PHY registers are retained after power collapse, meaning calibrating UFS PHY, start_serdes and polling PCS_ready_status can be done only when hba is powered_on, and not needed every time when phy_power_on is called during resume. Hence keep the code which enables PHY's regulators & clks in phy_power_on and move the rest steps into phy_calibrate function. Refactor the code to retain PHY regulators & clks in phy_power_on and move out rest of the code to new phy_calibrate function. Also move reset_control_assert to qmp_ufs_phy_calibrate to align with Hardware programming guide. Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Co-developed-by: Can Guo <quic_cang@quicinc.com> Signed-off-by: Can Guo <quic_cang@quicinc.com> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> Link: https://lore.kernel.org/r/20250526153821.7918-5-quic_nitirawa@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15phy: qcom-qmp-ufs: Rename qmp_ufs_enable and qmp_ufs_power_onNitin Rawat1-4/+4
Rename qmp_ufs_enable to qmp_ufs_power_on and qmp_ufs_power_on to qmp_ufs_phy_calibrate to better reflect their functionality. Also update function calls and structure assignments accordingly. Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Co-developed-by: Ram Kumar Dwivedi <quic_rdwivedi@quicinc.com> Signed-off-by: Ram Kumar Dwivedi <quic_rdwivedi@quicinc.com> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> Link: https://lore.kernel.org/r/20250526153821.7918-4-quic_nitirawa@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-15phy: cadence: Sierra: Add PCIe + USB PHY multilink configurationSwapnil Jakhade1-0/+180
Add register sequences for PCIe + USB multilink configuration for Sierra PHY. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250610130133.2102196-1-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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