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8 dayspinctrl: sunxi: dt: do not accumulate npins across probe attemptsPablo Mazzini1-0/+1
init_pins_table() adds to npins in the driver's static descriptor, so after a probe deferral the count doubles and the next probe fails with "pin 0 already registered". Reset it first. Signed-off-by: Pablo Mazzini <pmazzini@gmail.com> Fixes: f5e2cd34b12f ("pinctrl: sunxi: allow reading mux values from DT") Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
12 daysMerge tag 'pinctrl-qcom-fixes-for-v7.3-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into fixesLinus Walleij6-18/+43
Qualcomm pin control fixes for v7.3-rc7 - fix intr_target_width in several qualcomm pinctrl drivers - make direction changes exclusive in pinctrl-spmi-gpio - fix function issues in pinctrl-ipq5018 - add missing OF module alias to pinctrl-ipq5210 - split QUP1 SE2/SE3 into lane-pair functions Signed-off-by: Linus Walleij <linusw@kernel.org>
13 dayspinctrl: amd: Clear S4 wake bits when firmware has _AEIMario Limonciello1-0/+9
Commit ffe8a0c6b552 ("pinctrl-amd: Don't clear S4 wake bits at probe") preserves firmware-programmed S4 wake sources because some PCIe devices rely on them for Wake-on-LAN. The system that motivated that change does not expose ACPI GPIO events through _AEI. On a Chuwi CoreBook Plus, firmware exposes _AEI but also leaves the S4/S5 wake bit set for GPIO 24. This causes the machine to power back on immediately after shutdown even though Wake-on-LAN is not enabled. GPIO register dumps show that the only relevant difference is bit 15 on GPIO 24. Clearing that bit makes the machine remain off. GPIO 24 is not itself listed in _AEI, so _AEI is not a per-pin indication of which pins the OS manages; it is a platform level signal of which wake model the firmware follows. Use that signal to decide what to clear. Continue clearing S0i3/S3 bits on every system. Clear S4 bits when firmware exposes _AEI, indicating that the platform hands GPIO events to the OS, but preserve S4 bits when _AEI is absent so that firmware-programmed sources such as PCIe PME that bypass the GPIO IRQ wake API keep working. A platform that exposes _AEI for some pins while routing a wake capable device through a raw GPIO not listed in _AEI would lose that wake source unless firmware re-arms it during the sleep transition. No such system has been reported. Fixes: ffe8a0c6b552 ("pinctrl-amd: Don't clear S4 wake bits at probe") Reported-by: Olzhas Marat <marat.olzhas@gmail.com> Closes: https://bugzilla.kernel.org/show_bug.cgi?id=222041 Cc: stable@vger.kernel.org Tested-by: Olzhas Marat <marat.olzhas@gmail.com> Reviewed-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-10-06pinctrl: qcom: ipq5018: replace gcc_plltest with pwm2 on gpio12Adriel Santos1-3/+3
The pingroup table has gcc_plltest at function 5 of gpio12 and does not offer pwm2 on that pin, so the pinmux core rejects a request for pwm2 on gpio12 as an invalid group. On the hardware, function 5 of gpio12 carries the PWM2 output: the Xiaomi AX3000T v2 drives its blue status LED from PWM2 on gpio12. The vendor kernel shipped on that router (Linux 4.4, stock firmware 2.0.28) has pwm2 in this slot. Its pingroup table, as read from the firmware image, lists these functions for gpio12: gpio, blsp0_spi, blsp0_i2c, blsp1_uart0, _, pwm2, qdss_tracedata_a, _, _, _ and has pwm3 at function 4 of gpio13, matching commit c6c159fcdb4e ("pinctrl: qcom: ipq5018: add missing pwm3 function on gpio13"). Measured on the board: with gpio12 set to each of the 16 function values in turn, and PWM2 held at 0% and then at 100% duty, the pad level read back from GPIO_IN follows PWM2 only at function 5. There it does not follow PWM channels 0, 1 or 3, and the LED switches with PWM2. Functions 4 and 7, which the table leaves empty, do not carry PWM2. Put pwm2 in function 5 of gpio12 and list gpio12 in pwm2_groups. Drop gpio12 from gcc_plltest_groups: none of its functions is gcc_plltest any more, and selecting it would trigger the WARN_ON() in msm_pinmux_set_mux(). Fixes: 725d1c891658 ("pinctrl: qcom: Add IPQ5018 pinctrl driver") Assisted-by: LLM Signed-off-by: Adriel Santos <adriel@adriel.eu> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://patch.msgid.link/20261002160958.908424-1-adriel@adriel.eu Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-10-01pinctrl: qcom: ipq5018: update PWM groups and corresponding pin functionsGeorge Moussalem1-6/+6
On multiple Linksys routers, GPIOs 1, 30, and 46 drive the PWM LED on the PWM1, PWM3, and PWM0 channels, respectively. Update the corresponding PWM groups to include these GPIOs and allocate the PWM functions to empty slots in the relevant pin groups. Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://patch.msgid.link/20260928-ipq5018-pwm-functions-v2-1-87bbcd706bc6@outlook.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-09-28pinctrl: qcom: spmi-gpio: make direction changes exclusiveShawn Guo1-8/+29
Neither direction callback clears the opposite buffer: .direction_output() only packs PIN_CONFIG_LEVEL and .direction_input() only packs PIN_CONFIG_INPUT_ENABLE. As pmic_gpio_populate() seeds input_enabled and output_enabled from MODE_CTL, a pad left in DIGITAL_INPUT[_OUTPUT] by the bootloader ends up in DIGITAL_INPUT_OUTPUT whichever direction is requested. That leaves an input still driving the line, and makes pmic_gpio_get_direction() report an output as an input, which breaks consumers that read the direction back: reg-fixed-voltage regulator-wcn-core-vm-1p35: setup of GPIO (default) failed: -1 reg-fixed-voltage regulator-wcn-core-vm-1p35: error -EPERM: can't get GPIO Pack the opposite buffer's PIN_CONFIG_*_ENABLE along with the requested direction, so MODE_CTL becomes DIGITAL_INPUT or DIGITAL_OUTPUT, never both. pmic_gpio_config_set() writes the registers once after walking all configs, so this stays a single write. An open-drain or open-source output is the exception: it only drives one rail, so pmic_gpio_get() needs the input buffer to sample the line rather than return the value last written. Program the input buffer from pad->buffer_type, which gpiolib has already updated via PIN_CONFIG_DRIVE_OPEN_DRAIN, and key pmic_gpio_get_direction() off output_enabled so such pads still read back as outputs. Genuinely bidirectional pads can still be described that way through pinconf; the gpiolib callbacks now mean what gpiolib says they mean. Fixes: 263447532463 ("pinctrl: qcom: spmi-gpio: implement .get_direction()") Assisted-by: LLM Reviewed-by: Linus Walleij <linusw@kernel.org> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Link: https://patch.msgid.link/20260927010913.1212600-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-09-28Merge tag 'v7.3-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into pinctrl-qcom/for-currentBartosz Golaszewski9-124/+190
Linux 7.3-rc5
2026-09-22pinctrl: qcom: ipq5018: add missing pwm3 function on gpio13Gilberto Conde1-2/+2
GPIO13 supports the PWM3 function at mux select value 4, but the pingroup table leaves that slot empty and gpio13 is not listed in pwm3_groups. Selecting pwm3 on gpio13 is therefore rejected by the pinmux core: ipq5018-tlmm: invalid group "gpio13" for function "pwm3" The GL.iNet GL-X2000 drives its fan from PWM3 on this pin, and the vendor firmware muxes it with select value 4: gpio13 : out low func4 8mA no pull Add pwm3 to the fourth function slot of gpio13 and list gpio13 in pwm3_groups. With this the pin muxes as expected: pin 13 (GPIO_13): device 1941010.pwm function pwm3 group gpio13 Fixes: 725d1c891658 ("pinctrl: qcom: Add IPQ5018 pinctrl driver") Signed-off-by: Gilberto Conde <gilbertorconde@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260921093419.2870168-1-gilbertorconde@gmail.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-09-21pinctrl: tegra238: Fix register bank for AON pin groupsPrathamesh Shete1-102/+102
The AON pin controller has a single register region and therefore, the bank defined in the tegra238_functions[] and tegra238_aon_groups[] for the AON pin groups must be 0. However, commit 25cac7292d49 ("pinctrl: tegra: Add Tegra238 pinmux driver") incorrectly specified the bank for these pins as 1 and not 0. This means that in the tegra_pinctrl_probe() function we use an invalid index when accessing the pmx->regs[] array which causes an incorrect address to be used for accessing the pinmux registers. Fix this by correcting the bank for the AON pin groups. Fixes: 25cac7292d49 ("pinctrl: tegra: Add Tegra238 pinmux driver") Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-09-18pinctrl: qcom: ipq5210: Publish the OF module aliashpp.iscas1-0/+1
The IPQ5210 TLMM platform driver can be a module and matches through ipq5210_tlmm_of_match. This table is not published for OF modalias matching. Publish the existing table, preserving arch_initcall ordering and the shared MSM pinctrl probe. Fixes: a549fe22376f ("pinctrl: qcom: Introduce IPQ5210 TLMM driver") Signed-off-by: hpp.iscas <hppiscas@163.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260905134340.67477-1-hppiscas@163.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-09-18pinctrl: qcom: nord: Split QUP1 SE2/SE3 into lane-pair functionsShawn Guo1-11/+23
QUP1 SE2 and SE3 pack all four of their lanes pair-wise onto only two pins each: lanes 0/1 (I2C SDA/SCL) at mux value 2 and lanes 2/3 (UART TX/RX) at mux value 1, on gpio127/gpio128 and gpio129/gpio130 respectively. Both mux values were named "qup1_se2" (respectively "qup1_se3"), so the two distinct lane pairs became indistinguishable. msm_pinmux_set_mux() stops at the first entry matching the requested function, which means mux value 1 was always selected and the I2C lanes could never be muxed out. In practice i2c9 and i2c10 got the UART lanes and did not work, while uart9 and uart10 happened to be muxed correctly. Give each lane pair its own function, following the _01/_23 naming already used for the same hardware arrangement by the shikra, eliza, hawi and maili TLMM drivers. Both functions still cover the full pin pair, so a single pinctrl state per protocol remains sufficient. Drop gpio129/gpio130 from the SE2 group list, since those pins belong to SE3 and were never reachable through the SE2 function. Also rename QUP1 SE2/SE3 functions in the binding doc accordingly. While at it, add missing "gpio", "qup3_se0_mira" and "qup3_se0_mirb" to the binding function enum to get the list complete. Fixes: c24dd0826f06 ("pinctrl: qcom: add the TLMM driver for the Nord platforms") Cc: stable@vger.kernel.org Assisted-by: LLM Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260830030201.135637-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-09-17pinctrl: qcom: qcs8300: Fix intr_target_widthKonrad Dybcio1-0/+1
The default width of the interrupt target field doesn't match the actual register layout. Fix it. Fixes: 0c4cd2cc87c8 ("pinctrl: qcom: add the tlmm driver for QCS8300 platforms") Assisted-by: LLM Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Link: https://patch.msgid.link/20260917-topic-tlmm_intr_width_fixes-v1-3-3bc1d056aa6b@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-09-17pinctrl: qcom: maili: Fix intr_target_widthKonrad Dybcio1-0/+1
The default width of the interrupt target field doesn't match the actual register layout. Fix it. Fixes: 251b53103a2e ("pinctrl: qcom: Add the tlmm driver for Maili platform") Assisted-by: LLM Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Link: https://patch.msgid.link/20260917-topic-tlmm_intr_width_fixes-v1-2-3bc1d056aa6b@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-09-17pinctrl: qcom: hawi: Fix intr_target_widthKonrad Dybcio1-0/+1
The default width of the interrupt target field doesn't match the actual register layout. Fix it. Fixes: 90700e10d2ad ("pinctrl: qcom: Add Hawi pinctrl driver") Assisted-by: LLM Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Link: https://patch.msgid.link/20260917-topic-tlmm_intr_width_fixes-v1-1-3bc1d056aa6b@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-09-17pinctrl: qcom: nord: fix GPIO interrupt target widthZhangfei Gao1-0/+1
The TARGET_PROC field in the Nord GPIO_INTR_CFG registers occupies bits 11:8. Describe it as four bits wide so the common Qualcomm pinctrl code clears the complete field before routing an interrupt to the application processor. Without intr_target_width, the common code uses its three-bit default mask. Since GPIO_INTR_CFG resets with TARGET_PROC set to 0xf (NONE), bit 11 remains set when the driver programs HMSS target 3. The resulting target is 0xb (HPASS_DSP_1), observed as an interrupt configuration value of 0xb1b instead of 0x31b. The GPIO interrupt status is consequently latched, but the HMSS TLMM summary interrupt at GIC SPI 208 is never asserted. This affects all Nord GPIO interrupts using the TLMM summary path, including the Ethernet PHY interrupts on GPIO55 and GPIO141. Fixes: c24dd0826f06 ("pinctrl: qcom: add the TLMM driver for the Nord platforms") Signed-off-by: Zhangfei Gao <zhangfei.gao@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Link: https://patch.msgid.link/20260916085720.771498-1-zhangfei.gao@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-09-16pinctrl: single: free the IRQ on domain creation failureMyeonghun Pak1-1/+2
pcs_irq_init_chained_handler() requests a shared IRQ on affected SoCs, but its domain creation failure path only removes a chained handler. That does not release the action installed by request_irq(). The probe can continue without interrupt support while leaving the shared IRQ action registered. Use pcs_irq_free() to undo the appropriate type of handler registration. At this point pcs->domain is NULL, so the helper only releases the parent IRQ handler. Then mark the IRQ invalid, as the other initialization error paths already do, to prevent another release from a later probe unwind or remove. This issue was identified during our ongoing static-analysis research while reviewing kernel code. Fixes: 3e6cee1786a1 ("pinctrl: single: Add support for wake-up interrupts") Cc: stable@vger.kernel.org Assisted-by: LLM Co-developed-by: Ijae Kim <ae878000@gmail.com> Signed-off-by: Ijae Kim <ae878000@gmail.com> Signed-off-by: Myeonghun Pak <mhun512@gmail.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-09-16pinctrl: sunxi: A523: fix voltage withstand encodingAndre Przywara4-2/+10
The Allwinner A523 uses the same GPIO voltage "withstand" programming (setting the input level voltage thresholds) as the previous SoCs, but for some odd reason inverts the encoding of 1.8V vs. 3.3V. Add a new bias voltage type to note this difference, and select it for the A523. At the same time also use the newer "CTL" version, which in addition allows to turn off the withstand programming for I/O voltages other than exact 1.8V or 3.3V (for instance for 2.5V sometimes used for Ethernet PHYs). The A523 has that enable register, but didn't use it so far. This fixes eMMC and reportedly Ethernet operation on some A523 boards. Fixes: 648be4cd9517 ("pinctrl: sunxi: Add support for the Allwinner A523") Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Per Larsson <per@palvencia.se> Tested-by: Juan Manuel Lopez Carrillo <juanmanuellopezcarrillo@gmail.com> Reviewed-by: Chen-Yu Tsai <wens@kernel.org> Tested-by: Chen-Yu Tsai <wens@kernel.org> # Fixes eMMC on Orange Pi 4A Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-09-16pinctrl: sunxi: keep a shadow copy of the data register output latchesIlya Titov2-15/+68
On Allwinner SoCs, reading a bank's data register returns the pin level, not the output latch, for pins that are muxed as inputs. Writing a GPIO therefore corrupts the output latches of all input-muxed pins in the same bank: the read-modify-write in sunxi_pinctrl_gpio_set() reads back their pin levels and writes those into their latches. This breaks emulated open-drain lines (e.g. a bit-banged I2C bus from i2c-gpio). Such a line is released high by muxing it as input and letting the pull-up raise it, so any concurrent GPIO write in the same bank stores 1 into its latch. Driving the line low afterwards is a non-atomic data-then-mux sequence in sunxi_pinctrl_gpio_direction_output(); if the poisoning write lands between the two steps, the pin actively drives high (push-pull) instead of low. Observed in practice as sporadic glitches on a T507 board bit-banging I2C on port E while other PE GPIOs are toggled. On a scope the failure is unmistakable: on a clock pulse where SCL should fall to GND, the line instead steps *above* its idle high level for the whole low phase — the pad drives a strong push-pull 3.3 V high, higher than the level the pull-up sustains on the loaded bus — before the next transition recovers it. The same can hit SDA, corrupting data instead of clocks. Steps to reproduce on any sunxi board with a bit-banged (i2c-gpio) bus: # background: toggle any other GPIO of the same bank, e.g. line 21 gpioset -c <chip> --toggle 100us 21=0 & # foreground: keep the bit-banged bus busy while :; do i2cdetect -y <bus> 0x50 0x57; done # watch SCL/SDA with a scope or logic analyzer: sporadic clock-low # phases driven high (above the pull-up level) instead of low The bank spinlock cannot help: the racing write is a perfectly valid whole-register RMW that faithfully writes back what the hardware returned. There are no set/clear registers on this IP to write a single bit atomically. Fix it the same way gpio-mmio handles hardware whose data register read does not return the output latch: keep a shadow copy of each bank's latches, base the read-modify-write on the shadow, and only write the register. The shadow is seeded from the hardware at probe time so pins left in output mode by the bootloader keep their state. Pins that reach output mode through the gpiolib paths write their value (and thereby their shadow bit) before the mux switch in sunxi_pinctrl_gpio_direction_output(); pins muxed to gpio_out directly through a pinmux node bypass that path, so sunxi_pmx_set() refreshes their shadow bit from the latch (readable once the pin is in output mode) to keep them driving their pre-existing level. Seeding the shadow reads the PIO registers at probe time, which requires the bus clock to be enabled. The clock was only requested at the very end of probe, after devm_pinctrl_register() had already claimed the pin hogs described in the device tree - which mux pins, and thus access registers, with the clock still gated. Move the request ahead of both. Boards whose bootloader leaves the PIO clock running are unaffected, which is why the pre-existing hog problem has gone unnoticed since commit 950707c0eb5c ("pinctrl: sunxi: add clock support"). Fixes: df7b34f4c3d2 ("pinctrl: sunxi: Fix gpio_set behaviour") Cc: stable@vger.kernel.org Signed-off-by: Ilya Titov <ilya.titov@wirenboard.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-09-14pinctrl: mpfs-mssio: use correct regmap function to set bank voltageConor Dooley1-2/+2
regmap_assign_bits() is not the correct function to use for an RMW operation, as it maps to regmap_set_bits() or regmap_clear_bits() and the former will never zero a bit. Use regmap_update_bits() instead, which will actually set the bank voltages to what have been requested. CC: stable@vger.kernel.org Fixes: 488d704ed7b7 ("pinctrl: add polarfire soc mssio pinctrl driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-09-14pinctrl: mpfs-mssio: fix width of unused bank voltage settingConor Dooley1-1/+1
The bank voltages are only 4 bits wide, so when a pin was unused the driver was not correctly interpreting it as being at zero volts, because the driver's value for unused had two extra set bits. CC: stable@vger.kernel.org Fixes: 488d704ed7b7 ("pinctrl: add polarfire soc mssio pinctrl driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-09-14pinctrl: generic: serialise pinctrl_generic_dt_node_to_map()Sarah Emery1-0/+4
pinctrl_generic_add_group() documents that the caller must take care of locking, and pinmux_generic_add_function() needs it too, but pinctrl_generic_dt_node_to_map() calls them without holding pctldev->mutex, and the core caller in create_pinctrl() does not take it either. The driver core calls pinctrl_bind_pins() before probing a device, so two devices that reference the same pin controller can run pinctrl_generic_dt_node_to_map() on one pctldev at the same time. Both `add` functions take the new selector from pctldev->num_groups or pctldev->num_functions, and radix_tree_insert() at that index. Two racing callers can read the same selector before either has inserted, so the second insert collides and fails: k1-pinctrl d401e000.pinctrl: error -EEXIST: error adding function pcie2-0-cfg k1-pinctrl d401e000.pinctrl: does not have pin group pcie0-0-cfg.pcie0-0-pins leaving one consumer without its pin configuration. This was hit on a SpacemiT K3 board, where PCIe devices probe in parallel against the single shared pin controller. Take pctldev->mutex across the whole function, so that the groups and the function referring are in a single critical section. Fixes: 43722575e5cd ("pinctrl: add generic functions + pins mapper") Signed-off-by: Sarah Emery <sarah.emery@canonical.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-09-14pinctrl: meson: Fix typo in s4 group nameSean Anderson1-1/+1
One of the i2c pin groups has some junk at the end. The name should be i2c2_scl_h1, and indeed that's the name used by i2c2_pins3 in meson-s4.dtsi. Fixes: 775214d389c25 ("pinctrl: meson: add pinctrl driver support for Meson-S4 Soc") Signed-off-by: Sean Anderson <sanderson@brivo.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-09-07pinctrl: qcom: ipq5210: Publish the OF module aliashpp.iscas1-0/+1
The IPQ5210 TLMM platform driver can be a module and matches through ipq5210_tlmm_of_match. This table is not published for OF modalias matching. Publish the existing table, preserving arch_initcall ordering and the shared MSM pinctrl probe. Fixes: a549fe22376f ("pinctrl: qcom: Introduce IPQ5210 TLMM driver") Signed-off-by: hpp.iscas <hppiscas@163.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260905134340.67477-1-hppiscas@163.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-09-07pinctrl: qcom: nord: Split QUP1 SE2/SE3 into lane-pair functionsShawn Guo1-11/+23
QUP1 SE2 and SE3 pack all four of their lanes pair-wise onto only two pins each: lanes 0/1 (I2C SDA/SCL) at mux value 2 and lanes 2/3 (UART TX/RX) at mux value 1, on gpio127/gpio128 and gpio129/gpio130 respectively. Both mux values were named "qup1_se2" (respectively "qup1_se3"), so the two distinct lane pairs became indistinguishable. msm_pinmux_set_mux() stops at the first entry matching the requested function, which means mux value 1 was always selected and the I2C lanes could never be muxed out. In practice i2c9 and i2c10 got the UART lanes and did not work, while uart9 and uart10 happened to be muxed correctly. Give each lane pair its own function, following the _01/_23 naming already used for the same hardware arrangement by the shikra, eliza, hawi and maili TLMM drivers. Both functions still cover the full pin pair, so a single pinctrl state per protocol remains sufficient. Drop gpio129/gpio130 from the SE2 group list, since those pins belong to SE3 and were never reachable through the SE2 function. Also rename QUP1 SE2/SE3 functions in the binding doc accordingly. While at it, add missing "gpio", "qup3_se0_mira" and "qup3_se0_mirb" to the binding function enum to get the list complete. Fixes: c24dd0826f06 ("pinctrl: qcom: add the TLMM driver for the Nord platforms") Cc: stable@vger.kernel.org Assisted-by: LLM Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260830030201.135637-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
2026-08-24Merge tag 'pinctrl-v7.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrlLinus Torvalds94-2701/+12417
Pull pin control updates from Linus Walleij: "Core changes: - Use the non-blocking mux_state_try_select() in the generic MUX pin control back-end - Free pin maps on pinctrl_generic_to_map() failure in the core helpers New hardware pin control: - Qualcomm Maili TLMM SoC, PMG1110 PMIC, and Eliza LPASS LPI TLMM SoC (this is for the low power audio, LPASS = Low Power Audio SubSystem portions) - Upboard support on top of the Intel pin controller - Apple T6030 and T6031 support (just compatible strings) - Samsung Exynos 8855 SoC - Mediatek MT6858 SoC - Rockchip RK3308B and RV1106 SoCs - Airoha EN7523 and AN7563 SoCs Improvements: - Qualcomm TLMM GPIOs are unconditionally marked as wakeup capable - Qualcomm improvements on top of the Qualcomm PDC (power domain controller) irqchip improvements from tglx:s tree - Qualcomm IPQ806x and IPQ9650 non-urgent pin grop fixups - The NPCM8xx driver has been put into shape fixing many pin and group definitions - Some non-urgent Tegra 264 pin assignments are fixed up - Some non-urgent fixups to Airoha AN7581 and AN7583 registers and pin assignments, missing features etc" * tag 'pinctrl-v7.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (130 commits) dt-bindings: pinctrl: Convert TI DA850 pupd to DT schema pinctrl: meson: sync some modify from A4 pinctrl: meson: a4: Add input enable pin configuration pinctrl: realtek: rtd1625: remove unused group name spdif_sel pinctrl: realtek: rtd1625: fix base_bit for VE4 GPIO 13 dt-bindings: pinctrl: microchip,pic32mzda-pinctrl: Convert to DT schema Revert "Merge branch 'ib-rsk7204' into devel" pinctrl: rockchip: Add RV1106 pinctrl support dt-bindings: pinctrl: rockchip: Add RV1106 compatible pinctrl: rockchip: Decode drive strength in the get function pinctrl: fix PINCTRL_GENERIC_MUX not always being selectable pinctrl: airoha: add support of an7563 SoC dt-bindings: pinctrl: airoha: add support of an7563 pin controller pinctrl: airoha: try to find chip scu node by phandle first pinctrl: airoha: add support of en7523 SoC dt-bindings: pinctrl: airoha: add support of en7523 pin controller pinctrl: airoha: an7583: add support for olt pinmux pinctrl: airoha: an7583: add support for pon_alt pinmux pinctrl: airoha: an7583: add support for npu_uart pinmux dt-bindings: pinctrl: airoha: an7583: add missed features ...
2026-08-18Merge tag 'v7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into gpio/for-nextBartosz Golaszewski8-22/+33
Linux 7.2
2026-08-16Merge tag 'pinctrl-qcom-updates-for-v7.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into develLinus Walleij8-13/+1734
Qualcomm pinctrl updates for v7.3-rc1 New drivers: - add pinctrl drivers for Maili TLMM and Elize LPASS LPI TLMM controllers Driver updates: - acknowledge interrupts for the PDC interrupt controller in pinctrl-msm - implement irq_get/set_irqchip_state() for pinctrl-msm - add support for a new model to Qualcomm pinctrl-spmi-gpio - drop some dead code from qcom pinctrl modules Devicetree bindings: - document new TLMM controllers and the new model for the SPMI GPIO Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-16Merge tag 'pinctrl-qcom-fixes-for-v7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into develLinus Walleij6-20/+27
Qualcomm pin control fixes for v7.2 - fix intr_target_width for summary interrupt routing in pinctrl-shikra Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-14pinctrl: meson: sync some modify from A4Xianwei Zhao1-4/+4
Set the drive strength before enabling the output to avoid enabling the output with an unintended drive strength. Also return the actual output enable state from PIN_CONFIG_OUTPUT_ENABLE instead of always reporting it as enabled. Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-14pinctrl: meson: a4: Add input enable pin configurationXianwei Zhao1-2/+12
Add support for PIN_CONFIG_INPUT_ENABLE in the Amlogic A4 pinctrl driver. Use the existing output enable control to configure the input enable state, since the hardware uses the same control with inverse semantics. Also update PIN_CONFIG_OUTPUT_ENABLE handling to return the actual output enable state instead of treating any non-zero value as enabled. Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-14pinctrl: realtek: rtd1625: remove unused group name spdif_selYu-Chun Lin1-1/+1
Remove the undefined "spdif_sel" from rtd1625_iso_spdif_in_coaxial_groups to clean up the code. Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-14pinctrl: realtek: rtd1625: fix base_bit for VE4 GPIO 13Yu-Chun Lin1-1/+1
Fix a typo in the base_bit of RTD1625_VE4_GPIO_13. It was incorrectly set to 18, which overlaps with GPIO 16. Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-11Merge tag 'intel-pinctrl-v7.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into develLinus Walleij3-1/+54
intel-pinctrl for v7.3-1 * Enable CPLD pin control on UP Xtreme i12 board * Miscellaneous cleanup Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-11Revert "Merge branch 'ib-rsk7204' into devel"Linus Walleij1-28/+0
This reverts commit d922b54e942ee9c798b0d688b025362a24d864ea, reversing changes made to 3f0245e23a176e78f00a760291b8e4f88d01d77e. The SH maintainer has indicated that he want to carry these changes in the SH tree instead, and need more time to review and merge the changes, so reverting it out from my tree. Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-10pinctrl: rockchip: Add RV1106 pinctrl supportSimon Glass2-0/+196
Add pinctrl support for the Rockchip RV1106, based on the vendor kernel in the Luckfox Pico SDK [1] at commit 824b817f8 (a Linux 5.10.160 kernel tree). Each GPIO bank has its own IO control (IOC) register block, referenced by the rockchip,grf phandle of the bank node; the register offsets are relative to the bank's own block. The drive strength uses the RK3568-style exponential encoding and only pins 0-6 of GPIO0 have drive-strength registers. The RV1103 is a package variant of the RV1106 with fewer pins and uses the same pin controller. [1] https://github.com/LuckfoxTECH/luckfox-pico Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://github.com/LuckfoxTECH/luckfox-pico Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-10pinctrl: rockchip: Decode drive strength in the get functionSimon Glass1-19/+19
The decoding of the 2-bit and 8-bit level drive-strength values sits in rockchip_set_drive_perpin(), where it is unreachable: the SoCs whose banks declare these drive types (RK3506 and RV1103B) take the early ctrl->type branch in the set path, and the read-and-decode logic in a set function has no purpose. Meanwhile rockchip_get_drive_perpin() lacks the decoding, so pin_config_get() and the debugfs output report -EINVAL for these SoCs. Move the two cases to rockchip_get_drive_perpin(), where they belong. Fixes: dbd2317d7b9f ("pinctrl: rockchip: Add rk3506 pinctrl support") Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: fix PINCTRL_GENERIC_MUX not always being selectableAlvin Šipraga1-1/+1
CONFIG_MULTIPLEXER can only be enabled indirectly. If it's not already enabled, then CONFIG_PINCTRL_GENERIC_MUX cannot be selected at all in menuconfig. That's because it depends on MULTIPLEXER. Follow similar consumers of the multiplexer core and select MULTIPLEXER instead. This way the driver will be visible in menuconfig as long as PINCTRL is selected. Fixes: 34acc5a8adfb ("pinctrl: add generic board-level pinctrl driver using mux framework") Signed-off-by: Alvin Šipraga <alvin.sipraga@analog.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: add support of an7563 SoCMikhail Kshevetskiy3-0/+1125
This patch adds support of Airoha an7563 SoC pin controller. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: try to find chip scu node by phandle firstMikhail Kshevetskiy5-3/+10
The "airoha,en7581-chip-scu" is not a good compatible string in the en7523 case. Let's search chip scu regmap with "airoha,chip-scu" phangle first and fallback to SoC specific chip scu compatible string on failure. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: add support of en7523 SoCMikhail Kshevetskiy3-0/+1166
This patch adds support of Airoha en7523 SoC pin controller. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: an7583: add support for olt pinmuxMikhail Kshevetskiy1-0/+18
Add support for olt pin function for olt pin group. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: an7583: add support for pon_alt pinmuxMikhail Kshevetskiy1-2/+14
Add support for pon pin function for pon_alt pin group. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: an7583: add support for npu_uart pinmuxMikhail Kshevetskiy1-1/+11
Add support for uart pin function for npu_uart pin group. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: an7583: rename registers to match its an7583 namesMikhail Kshevetskiy1-5/+5
In the an7581 case the register at 0x1FA20214 is called RG_GPIO_2ND_I2C_MODE. The same register in the an7583 case is called RG_SW_TOD_1PPS_MODE. Let's rename this register to avoid potential confuse. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: an7583: remove an7583 prefix from variable names and definitionsMikhail Kshevetskiy1-307/+307
We have only an7583 specific code in the pinctrl-an7583 kernel module, so an7583 prefix is not necessary anymore. Remove it. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: an7581: remove en7581 prefix from variable namesMikhail Kshevetskiy1-198/+198
We have only an7581 specific code in the pinctrl-an7581 kernel module, so 'en7581_' prefix is not necessary anymore. Remove it. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: split driver on shared code and SoC specific driversMikhail Kshevetskiy6-2374/+2999
Split combined an7581/an7583 source file on a * shared pinctrl code (pinctrl-airoha.c) * an7581 specific pinctrl driver (pinctrl-an7581.c) * an7583 specific pinctrl driver (pinctrl-an7583.c) Ininialization code was adapted a bit to work properly for shared and SoC specific cases. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: move common definitions to the separate headerMikhail Kshevetskiy2-270/+283
Let's move the SoC independent definitions and declarations of structures required for Airoha SoC-specific pinctrl drivers to a common header. Later we'll have several SoC-specific drivers, so this step is necessary. We will not move to the common header file other register addresses, register bitfields definitions and macroses that use SoC specific information. We will keep SoC specific definitions inside SoC specific files. No functional changes. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: statically allocate gpio regs structureMikhail Kshevetskiy1-46/+46
just a small refactoring to collect all gpio register information in the one statically allocated structure. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Linus Walleij <linusw@kernel.org>
2026-08-07pinctrl: airoha: remove not needed irq_type[] arrayMikhail Kshevetskiy1-14/+8
irq_type[] array inside airoha_pinctrl_gpiochip structure is not actually necessary. Use trigger type from 'struct irq_data' instead. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Acked-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
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