diff options
| author |   Evan Quan <evan.quan@amd.com> | 2020-06-04 11:15:12 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2020-07-01 01:59:16 -0400 |
| commit | 02cf91c113eacd069d58633871a1ccf3b17a33d6 (patch) | |
| tree | 8daac3d05b1a4e05f1647dd4c853aafb69205431 | |
| parent | drm/amd/powerplay: clean up the overdrive settings (diff) | |
drm/amd/powerplay: postpone operations not required for hw setup to late_init
So that we do not need to perform those unnecessary operations again on
resume.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 57 |
1 files changed, 28 insertions, 29 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c index 95c061d0a8dc..02e660d09753 100644 --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c @@ -769,10 +769,36 @@ static int smu_late_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct smu_context *smu = &adev->smu; + int ret = 0; if (!smu->pm_enabled) return 0; + ret = smu_set_default_od_settings(smu); + if (ret) + return ret; + + /* + * Set initialized values (get from vbios) to dpm tables context such as + * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each + * type of clks. + */ + ret = smu_populate_smc_tables(smu); + if (ret) + return ret; + + ret = smu_init_max_sustainable_clocks(smu); + if (ret) + return ret; + + ret = smu_populate_umd_state_clk(smu); + if (ret) + return ret; + + ret = smu_get_power_limit(smu, &smu->default_power_limit, false, false); + if (ret) + return ret; + smu_get_unique_id(smu); smu_handle_task(&adev->smu, @@ -1178,39 +1204,10 @@ static int smu_smc_table_hw_init(struct smu_context *smu, if (ret) return ret; - /* - * Set initialized values (get from vbios) to dpm tables context such as - * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each - * type of clks. - */ - if (initialize) { - ret = smu_populate_smc_tables(smu); - if (ret) - return ret; - - ret = smu_init_max_sustainable_clocks(smu); - if (ret) - return ret; - } - ret = smu_override_pcie_parameters(smu); if (ret) return ret; - ret = smu_set_default_od_settings(smu); - if (ret) - return ret; - - if (initialize) { - ret = smu_populate_umd_state_clk(smu); - if (ret) - return ret; - - ret = smu_get_power_limit(smu, &smu->default_power_limit, false, false); - if (ret) - return ret; - } - /* * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. */ @@ -1428,6 +1425,8 @@ int smu_reset(struct smu_context *smu) if (ret) return ret; + ret = smu_late_init(adev); + return ret; } |