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authorNagarjuna Kristam <nkristam@nvidia.com>2019-09-17 12:26:44 +0530
committerThierry Reding <treding@nvidia.com>2019-10-29 20:30:06 +0100
commit05705c721591d0f8bdd1ea126f5d16176607c415 (patch)
treef0c6339001a91950881990ad5cf4ecc46c297819
parentarm64: tegra: Enable XUSB pad controller on Jetson TX2 (diff)
arm64: tegra: Enable SMMU for XUSB host on Tegra186
Enabling the SMMU for XUSB host allows buffers to be mapped through the ARM SMMU, which helps protecting the system from rogue memory accesses by the XUSB host. Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra186.dtsi1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 47cd831fcf44..abdc81f555b9 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -525,6 +525,7 @@
<0x0 0x03538000 0x0 0x1000>;
reg-names = "hcd", "fpci";
+ iommus = <&smmu TEGRA186_SID_XUSB_HOST>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;