diff options
| author |   Uma Shankar <uma.shankar@intel.com> | 2017-02-08 16:20:51 +0530 |
|---|---|---|
| committer |   Jani Nikula <jani.nikula@intel.com> | 2017-02-15 17:32:57 +0200 |
| commit | 06a20d2d2d4187b9bc1a4c2f62e989a97a086a76 (patch) | |
| tree | 82cfb4f754f3f8644b4a1e0aa5abd0a0103053b9 | |
| parent | drm/i915: Check for platform specific GPIO config (diff) | |
| download | linux-dev-06a20d2d2d4187b9bc1a4c2f62e989a97a086a76.tar.xz linux-dev-06a20d2d2d4187b9bc1a4c2f62e989a97a086a76.zip | |
drm/i915: Fix PLL 8x/3 divider for MIPI video mode
MIPI Video Mode for high res panels (requiring dual link), need a
8X/3 divider to be programmed as 0x2. Modifying the same
in this patch.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1486551058-22596-3-git-send-email-vidya.srinivas@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dsi_pll.c | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c index 61440e5c2563..3a7308681360 100644 --- a/drivers/gpu/drm/i915/intel_dsi_pll.c +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c @@ -416,11 +416,7 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port, rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2; rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2; - /* As per bpsec program the 8/3X clock divider to the below value */ - if (dev_priv->vbt.dsi.config->is_cmd_mode) - mipi_8by3_divider = 0x2; - else - mipi_8by3_divider = 0x3; + mipi_8by3_divider = 0x2; tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider); tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div); |