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authorPrabhakar Kushwaha <prabhakar@freescale.com>2011-05-23 15:53:25 +0530
committerKumar Gala <galak@kernel.crashing.org>2011-06-27 08:31:09 -0500
commit08871c097ea5a11c95146ba8310272571d2bbfc4 (patch)
tree7f01f76e7970abde1933e57aaac83b5deeec3aa8
parentpowerpc/85xx: add board support for the Freescale hypervisor (diff)
downloadlinux-dev-08871c097ea5a11c95146ba8310272571d2bbfc4.tar.xz
linux-dev-08871c097ea5a11c95146ba8310272571d2bbfc4.zip
powerpc/85xx: Add host-pci(e) bridge only for RC
FSL PCIe controller can act as agent(EP) or host(RC). Under Agent(EP) mode the controller will be configured by the host system. So its not required to be registered with the PCI(e) sub-system. We only register the controller if its configured in host(RC) mode. Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
-rw-r--r--arch/powerpc/sysdev/fsl_pci.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index b4d6046deff8..80b8b7a04454 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -330,6 +330,7 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
struct pci_controller *hose;
struct resource rsrc;
const int *bus_range;
+ u8 progif;
if (!of_device_is_available(dev)) {
pr_warning("%s: disabled\n", dev->full_name);
@@ -360,6 +361,18 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
PPC_INDIRECT_TYPE_BIG_ENDIAN);
+
+ early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
+ if ((progif & 1) == 1) {
+ /* unmap cfg_data & cfg_addr separately if not on same page */
+ if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
+ ((unsigned long)hose->cfg_addr & PAGE_MASK))
+ iounmap(hose->cfg_data);
+ iounmap(hose->cfg_addr);
+ pcibios_free_controller(hose);
+ return 0;
+ }
+
setup_pci_cmd(hose);
/* check PCI express link status */