diff options
| author |   Evan Quan <evan.quan@amd.com> | 2019-11-14 16:58:31 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2019-11-19 10:12:51 -0500 |
| commit | 09ba2e7d68f8c24ef3c7469d6632818c535bcb2c (patch) | |
| tree | 968560c1f032df57f8771a83778657a2bea22b58 | |
| parent | drm/amd/powerplay: issue no PPSMC_MSG_GetCurrPkgPwr on unsupported ASICs (diff) | |
drm/amd/powerplay: correct fine grained dpm force level setting
For fine grained dpm, there is only two levels supported. However
to reflect correctly the current clock frequency, there is an
intermediate level faked. Thus on forcing level setting, we
need to treat level 2 correctly as level 1.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index b759226ec67a..bc44bc4e0b9d 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -886,6 +886,12 @@ static int navi10_force_clk_levels(struct smu_context *smu, case SMU_UCLK: case SMU_DCEFCLK: case SMU_FCLK: + /* There is only 2 levels for fine grained DPM */ + if (navi10_is_support_fine_grained_dpm(smu, clk_type)) { + soft_max_level = (soft_max_level >= 1 ? 1 : 0); + soft_min_level = (soft_min_level >= 1 ? 1 : 0); + } + ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq); if (ret) return size; |