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| author |   Alex Helms <alexander.helms.jy@renesas.com> | 2022-09-12 11:36:12 -0700 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2022-09-30 17:34:20 -0700 |
| commit | 09d1855656dad04127aee195baf2eedae029175d (patch) | |
| tree | e3af56557df45f9fc76ac97a56cde964c2fdb3b4 | |
| parent | Linux 6.0-rc1 (diff) | |
| download | linux-dev-09d1855656dad04127aee195baf2eedae029175d.tar.xz linux-dev-09d1855656dad04127aee195baf2eedae029175d.zip | |
dt-bindings: Renesas versaclock7 device tree bindings
Renesas Versaclock7 is a family of configurable clock generator ICs
with fractional and integer dividers. This driver has basic support
for the RC21008A device, a clock synthesizer with a crystal input and
8 outputs. The supports changing the FOD and IOD rates, and each
output can be gated.
Signed-off-by: Alex Helms <alexander.helms.jy@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220912183613.22213-2-alexander.helms.jy@renesas.com
Tested-by: Saeed Nowshadi <saeed.nowshadi@amd.com>
[sboyd@kernel.org: Rename nodes in example to generic names]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| -rw-r--r-- | Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml | 64 | ||||
| -rw-r--r-- | MAINTAINERS | 5 |
2 files changed, 69 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml b/Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml new file mode 100644 index 000000000000..8d4eb4475fc8 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,versaclock7.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Versaclock7 Programmable Clock Device Tree Bindings + +maintainers: + - Alex Helms <alexander.helms.jy@renesas.com> + +description: | + Renesas Versaclock7 is a family of configurable clock generator and + jitter attenuator ICs with fractional and integer dividers. + +properties: + '#clock-cells': + const: 1 + + compatible: + enum: + - renesas,rc21008a + + reg: + maxItems: 1 + + clocks: + items: + - description: External crystal or oscillator + + clock-names: + items: + - const: xin + +required: + - '#clock-cells' + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + vc7_xin: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <49152000>; + }; + + i2c@0 { + reg = <0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + + vc7: clock-controller@9 { + compatible = "renesas,rc21008a"; + reg = <0x9>; + #clock-cells = <1>; + clocks = <&vc7_xin>; + clock-names = "xin"; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 8a5012ba6ff9..c1b1c7ead11d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17441,6 +17441,11 @@ S: Maintained F: Documentation/devicetree/bindings/mtd/renesas-nandc.yaml F: drivers/mtd/nand/raw/renesas-nand-controller.c +RENESAS VERSACLOCK 7 CLOCK DRIVER +M: Alex Helms <alexander.helms.jy@renesas.com> +S: Maintained +F: Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml + RESET CONTROLLER FRAMEWORK M: Philipp Zabel <p.zabel@pengutronix.de> S: Maintained |