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authorMikko Perttunen <mperttunen@nvidia.com>2022-06-27 17:20:07 +0300
committerThierry Reding <treding@nvidia.com>2022-07-08 16:27:53 +0200
commit0ae4ae9158f32fd77e8736da0585d8aff5a3b9d9 (patch)
treeb4a8c9cc8a1bf034749247adfc608268d51d43f8
parentgpu: host1x: Add MLOCK release code on Tegra234 (diff)
downloadlinux-dev-0ae4ae9158f32fd77e8736da0585d8aff5a3b9d9.tar.xz
linux-dev-0ae4ae9158f32fd77e8736da0585d8aff5a3b9d9.zip
gpu: host1x: Use RESTART_W to skip timed out jobs on Tegra186+
When MLOCK enforcement is enabled, the 0-word write currently done is rejected by the hardware outside of an MLOCK region. As such, on these chips, which also have the newer, more convenient RESTART_W opcode, use that instead to skip over the timed out job. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
-rw-r--r--drivers/gpu/host1x/cdma.c19
1 files changed, 17 insertions, 2 deletions
diff --git a/drivers/gpu/host1x/cdma.c b/drivers/gpu/host1x/cdma.c
index 765e5aa64eb6..bb1f3c746be4 100644
--- a/drivers/gpu/host1x/cdma.c
+++ b/drivers/gpu/host1x/cdma.c
@@ -457,9 +457,24 @@ syncpt_incr:
* to offset 0xbad. This does nothing but
* has a easily detected signature in debug
* traces.
+ *
+ * On systems with MLOCK enforcement enabled,
+ * the above 0 word writes would fall foul of
+ * the enforcement. As such, in the first slot
+ * put a RESTART_W opcode to the beginning
+ * of the next job. We don't use this for older
+ * chips since those only support the RESTART
+ * opcode with inconvenient alignment requirements.
*/
- mapped[2*slot+0] = 0x1bad0000;
- mapped[2*slot+1] = 0x1bad0000;
+ if (i == 0 && host1x->info->has_wide_gather) {
+ unsigned int next_job = (job->first_get/8 + job->num_slots)
+ % HOST1X_PUSHBUFFER_SLOTS;
+ mapped[2*slot+0] = (0xd << 28) | (next_job * 2);
+ mapped[2*slot+1] = 0x0;
+ } else {
+ mapped[2*slot+0] = 0x1bad0000;
+ mapped[2*slot+1] = 0x1bad0000;
+ }
}
job->cancelled = true;